Dave's PCF WIP: Paragraphs

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Actions	Application	Content	Paragraph Number	Notes	Modified
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View Edit Delete	US-8380915-A1	In another embodiment, the read data pipeline 108 includes a read program module 338 that includes one or more user-definable functions within the read data pipeline 108. The read program module 338 has similar characteristics to the write program module 310 and allows a user to provide custom functions to the read data pipeline 108. The read program module 338 may be located as shown in FIG. 3A, may be located in another position within the read data pipeline 108, or may include multiple parts in multiple locations within the read data pipeline 108. Additionally, there may be multiple read program modules 338 within multiple locations within the read data pipeline 108 that operate independently. One of skill in the art will recognize other forms of a read program module 338 within a read data pipeline 108. As with the write data pipeline 106, the stages of the read data pipeline 108 may be rearranged and one of skill in the art will recognize other orders of stages within the read data pipeline 108.	163	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the read data pipeline 108 includes a decompression module 336 that decompresses a data segment formatted by the depacketizer 324. In one embodiment, the decompression module 336 uses compression information stored in one or both of the packet header and the container label to select a complementary routine to that used to compress the data by the compression module 312. In another embodiment, the decompression routine used by the decompression module 336 is dictated by the device requesting the data segment being decompressed. In another embodiment, the decompression module 336 selects a decompression routine according to default settings on a per data structure type or data structure class basis. A first packet of a first object may be able to override a default decompression routine and a second packet of a second data structure of the same data structure class and data structure type may use the default decompression routine and a third packet of a third data structure of the same data structure class and data structure type may use no decompression.	162	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the read data pipeline 108 includes a decryption module 334 that decrypts a data segment formatted by the depacketizer 324 prior to sending the data segment to the output buffer 330. The data segment may be decrypted using an encryption key received in conjunction with the read request that initiates retrieval of the requested packet received by the read synchronization buffer 328. The decryption module 334 may decrypt a first packet with an encryption key received in conjunction with the read request for the first packet and then may decrypt a second packet with a different encryption key or may pass the second packet on to the next stage of the read data pipeline 108 without decryption. When the packet was stored with a non-secret cryptographic nonce, the nonce is used in conjunction with an encryption key to decrypt the data packet. The encryption key may be received from a client 114, a computer 112, key manager, or other device that manages the encryption key to be used by the solid-state storage controller 104.	161	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In a further embodiment, the inverse bias module 332 converts the biased packets back to their original source data without using an indicator. Instead of using an indicator, the inverse bias module 332 may implement an algorithm that is the inverse operation of the bias module 318. This algorithm may inverse the bias for each data packet received and/or a select number of data packets received. In the depicted embodiment, the inverse bias module 332 is located between the ECC decoder 322 and the depacketizer 324. In a further embodiment, the inverse bias module 332 may be located elsewhere in the read data pipeline 108, based on the location of the bias module 318 in the write data pipeline 106.	160	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the read data pipeline 108 includes an inverse bias module 332 that receives one or more requested biased packets from the ECC decoder 322, either directly or indirectly, and converts the one or more requested packets back to their original source form by reversing the biasing process of the bias module 318 prior to sending the one or more requested packets to the depacketizer 324. In one embodiment, the inverse bias module 332 may use one or more indicators stored by the bias module 318 to convert the biased packets back to their original source data. In certain embodiments, the inverse bias module 332 may provide a known bias, a read bias, and/or a deviation from a known bias for a packet or other data set to the configuration module 352, as described below with regard to FIG. 3B.	159	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the write buffer 320 is a ping-pong buffer where one side of the buffer is filled and then designated for transfer at an appropriate time while the other side of the ping-pong buffer is being filled. In another embodiment, the write buffer 320 includes a first-in first-out (“FIFO”) register with a capacity of more than a virtual page of data segments. One of skill in the art will recognize other write buffer 320 configurations that allow a virtual page of data to be stored prior to writing the data to the solid-state storage media 110.	130	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the solid-state storage controller 104 may read data in a data packet from multiple channels, storage elements, dies, chips, physical erase blocks (“PEBs”), groupings of storage cells, or the like within the solid-state storage media 110, each of which may have independent read voltage thresholds. The manufacturer of the channels, storage elements, dies, chips, and/or grouping of storage cells may make the read voltage thresholds for each channel, storage element, die, chip, and/or grouping of storage cells independently adjustable by the solid-state storage controller 104. Alternatively, or in addition, the manufacturer of the channels, storage elements, dies, chips, and/or grouping of storage cells may make the read voltage thresholds for groups of channels, groups of storage elements, groups of die, groups of chips, and/or groups of groupings of storage cells adjustable by the solid-state storage controller 104 as separate groups.	157	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The configuration module 352, in one embodiment, may monitor the read bias of each packet read and compare the bias of the packet or other data set to the known bias in response to a read request. In a further embodiment, the configuration module 352 may monitor the read bias of each packet read and may compare the bias of the data set or packet to the known bias in response to a data error, such as, for example, an uncorrectable bit error that the ECC decoder 322 cannot correct, or the like. In a further embodiment, the configuration module 352 may not monitor the read bias of each packet read and may determine and compare the bias of the data set or packet to the known bias exclusively in response to a data error. As described below with regard to the proactive configuration module 424 of FIGS. 4 and 5, in certain embodiments, the configuration module 352 sets or adjusts a read voltage threshold or other configuration parameter proactively, based on storage media characteristics instead of, or in addition to, adjustments based on read data sets or packets.	156	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The configuration module 352, in one embodiment, may request that the data set be re-read with the new read voltage threshold. The configuration module 352 may determine whether the re-read data set has a read bias that deviates from the known bias, and may iteratively adjust the read voltage threshold to a new read voltage threshold until the read bias of the data set no longer deviates from the known bias more than a threshold amount (which may be zero), until the ECC decoder 322 can correct errors in the data set, or the like. In one embodiment, the configuration module 352 stores the new read voltage threshold such that the new read voltage threshold is persistent for subsequent data reads from the solid-state storage media 110. In a further embodiment, the solid-state storage media 110 stores the new read voltage threshold for subsequent data reads.	155	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The configuration module 352, in one embodiment, determines that a read bias for the data set or packet deviates from the known bias, and determines a direction of deviation for the data set based on a difference between the read bias and the known bias. In a further embodiment, the configuration module 352 adjusts the read voltage threshold, or another read threshold such as a resistivity threshold, for storage cells corresponding to the data set based on the direction of deviation. For example, in one embodiment, the configuration module 352 may lower the read voltage threshold from the previous read voltage threshold to a new read voltage threshold for the storage cells if the data set has more binary zeroes than expected based on the known bias. For MLC storage cells, in one embodiment, a data set may include data from different addresses, different pages, or the like so that the data set includes all data that the associated storage cells store. The configuration module 352 may base a read voltage threshold adjustment on known characteristics of the storage cells, such as an encoding type used for the storage cells, based on a physical and/or electrical architecture of the storage cells, or the like. In a further embodiment, the configuration module 352 may transform, translate, or combine data from different addresses or pages to facilitate a determination of a known bias, a read bias, and/or a deviation from a known bias for MLC storage cells. In another embodiment, for MLC storage cells, the configuration module 352 may adjust a read voltage threshold for the MLC storage cells based on a subset of the data stored by the MLC storage cells.	154	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the data set or packet that the configuration module 352 receives has a known bias. The data set or packet has a known bias for one of at least three reasons. First, the data set or packet may have a known bias because the bias module 318 biased the data set or packet when the data set or packet was written. In one embodiment, the bias module 318 and/or the inverse bias module 332 cooperate with the configuration module 352, communicating the known bias to the configuration module 352. Second, the data set or packet may have a known bias because the data set or packet is read from a virgin, unwritten region of the solid-state storage media 110. For example, in one embodiment, virgin, unwritten regions of the solid-state storage media 110 may typically have a known bias of exclusively binary ones or exclusively binary zeroes in an unwritten state. Third, the data set or packet may have a known bias because the ECC decoder 322 has corrected the data set or packet and has determined the original, correct values of one or more bits of the data set that were in error. The correct values for the bits in the data set comprise this known bias. A deviation from the known bias caused by errors in the data set is an error bias.	153	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The configuration module 352, in one embodiment, uses a known bias of the data set or packet from the solid-state storage media 110 to adjust the read voltage threshold or other configuration parameter. As described above with regard to the bias module 318, a bias is a preference, probability, tendency, or desirability of values for bits within a set of bits to exhibit a specific data pattern. A bias may be a natural property, a designed attribute, a property of performing an operation on storage media, or a random occurrence. A bias may be toward binary ones, toward binary zeroes, toward a balance of binary ones and zeroes, toward a certain binary value for certain bits, toward a specific ratio of binary ones and binary zeroes, toward a binary pattern, or the like.	152	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The read voltage levels of storage cells, and other configuration parameters, can also shift over time, due to leakage and other disturbances of the solid-state storage media 110. The rate of leakage can also increase with the wear and age of the solid-state storage media 110. If the read voltage level of a storage cell shifts past the read voltage threshold, a data error occurs, as the value of the data read from the storage cell is different than the value of the data written to the storage cell. The configuration module 352, in one embodiment, adjusts a read voltage threshold or other configuration parameter for one or more storage cells from the solid-state storage media 110 to compensate for shifts in the read voltage levels of the storage cells. By proactively and/or dynamically adjusting read voltage thresholds, the configuration module 352 can increase the retention rate for and/or the reliability of data stored in the solid-state storage media 110 and extend the useable lifetime of the solid-state storage media 110 itself, improving the utility of the solid-state storage media 110.	151	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, instead of referring to a boundary between discrete values, a read voltage threshold comprises a range of voltages (a maximum and a minimum) that indicate a value. A voltage threshold that is a range can be adjusted by changing the boundary at either end, or at both ends, of the range. The read voltage thresholds or other configuration parameters for the solid-state storage media 110, in one embodiment, are initially set at a default level that may be defined by a manufacturer. Often such configuration parameter default levels are set to accommodate a large range of general purpose uses of the solid-state storage media 110. Advantageously, embodiments of the configuration module 352 allow the solid-state storage media 110 to be used most optimally based on more specific use characteristics. The configuration module 352, in certain embodiments, overrides the default level for one or more configuration parameters, setting the one or more configuration parameters to a different level based on storage media characteristics of the solid-state storage media 110. The configuration module 352 may set the configuration parameters to a level that decreases the amount of errors that the solid-state storage media 110 encounters when compared to the default level, to a level that increases the amount of errors that may be detected and corrected when compared to the default level, to a level that increases the number of input/output operations per second (“TOPS”) of the solid-state storage media 110 when compared to the default level, to a level that increases the usable life of the solid-state storage media 110 when compared to the default level, and/or that otherwise improves the utility of the solid-state storage media 110 when compared to the default level.	150	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the write data pipeline 106 also includes a write synchronization buffer 308 that buffers packets received from the ECC encoder 304 prior to writing the packets to the solid-state storage media 110. The write synchronization buffer 308 is located at a boundary between a local clock domain and a solid-state storage clock domain and provides buffering to account for the clock domain differences. In other embodiments, synchronous solid-state storage media 110 may be used and synchronization buffers 308328 may be eliminated.	102	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the bias module 318 biases source data to reduce inter-cell interference as a separate step performed separately from, instead of, or in addition to other biasing techniques. For example, upon flipping, whitening, compressing, relocating, and/or otherwise biasing source data, separate blocks of source data may still exhibit patterns that cause inter-cell interference, and the bias module 318 may bias one or more of the separate blocks of source data toward a pattern that minimizes inter-cell interference, or the like.	111	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For certain types of storage cells, such as SLC flash memory, the voltage level of a storage cell and associated voltage differentials between storage cells may be based on a single bit value for each storage cell and biasing data may include biasing toward a binary pattern with minimal transitions between binary one values and binary zero values within a data packet and/or within a physical region of storage cells. For other types of storage cells, such as MLC flash memory, the voltage level of a storage cell and associated voltage differentials between storage cells may be based on groups of bits forming a sub-pattern or symbol, and biasing data may include biasing toward a binary pattern with minimal transitions between certain sub-patterns or symbols. One example of using sub-patterns or symbols includes binary or Gray-code mapping of multiple binary values to associated charge levels within MLC storage cells. The bits stored by a single MLC storage cell, in certain embodiments, may not have adjacent addresses, but may be stored on different physical pages, logical pages, or the like.	110	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In addition to local types of inter-cell interference, larger multi-cell structures, such as bit strings, word lines, or the like, may experience inter-cell interference. Certain stripes or other patterns in data, such as stripes of binary ones or of binary zeroes, may interfere with the accuracy or effectiveness of sense amplifiers and/or other management circuitry for these larger, multi-cell structures, and it may be advantageous to bias data away from such stripes or other patterns.	109	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, a bias of one or more storage cells may be influenced by or based on a state of other storage cells physically adjacent to or otherwise in proximity to the one or more storage cells. For example, it may be desirable to bias data stored in storage cells to minimize inter-cell interference between the storage cells and other storage cells, or the like. Inter-cell interference can be caused by voltage differentials between physically adjacent storage cells and, in certain embodiments, biasing data to reduce or minimize the voltage differentials between storage cells based on a physical geometry of the storage cells can reduce inter-cell interference. In one embodiment, storage cells of the solid-state storage media 110 may have a bias toward a binary pattern that satisfies a predefined voltage differential threshold between the storage cells and other physically adjacent storage cells, or the like.	108	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	For example, in one embodiment, the storage cells of the storage elements 216, 218, 220 may each store a binary value of one upon delivery from a manufacturer, and may each be erased to a value of one prior to being programmed, or written to, as is typical with flash memory. In another embodiment, the storage cells of the storage elements 216, 218, 220 may be biased toward binary zeroes, toward a balance or equal amount of binary ones and zeroes, toward a certain binary value for a plurality of bits, toward a binary pattern, or the like.	107	Added by DJM 3 2021	3/12/21, 12:00 AM

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