Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US-8380915-A1	In other embodiments, the configuration module 352 may receive a data set from the solid-state storage media 110, either directly or indirectly, to determine configuration parameters for corresponding storage cells in a closed loop manner, with read data sets as feedback from the storage cells. In certain embodiments, the configuration module 352 may receive one or more requested biased packets from the ECC decoder 322. In a further embodiment, the configuration module 352 may receive a data set from the read synchronization buffer 328, directly from the storage I/O bus 210, from the inverse bias module 332, or otherwise. The configuration module 352 is described in greater detail with regard to FIG. 4. Another embodiment, where the configuration module 352 receives input from both the ECC decoder 322 and the inverse bias module 332 is described below with regard to FIG. 3B.	145	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the solid-state storage controller 104 includes a configuration module 352 that sets and adjusts configuration parameters for the solid-state storage media 110, such as read voltage thresholds and the like. In a further embodiment, the configuration module 352 may be integrated with the solid-state storage media 110 such that it operates independently from the read data pipeline 108 and/or the write data pipeline 106. In certain embodiments, as described in greater detail below with regard to the proactive configuration module 424 of FIG. 4 and FIG. 5, the configuration module 352 proactively determines one or more configuration parameters for storage cells of the solid-state storage media 110 based on storage media characteristics for the storage cells in an open loop manner, with little or no feedback from the storage cells. In the depicted embodiment, the configuration module 352 is in communication with the storage control bus 212 and the storage bus controller 348 to configure storage cells of the solid-state storage media 110 to use various configuration parameters. In another embodiment, the configuration module 352 manages configuration parameters and/or settings for the solid-state storage controller 104 and or for the solid-state storage device 102.	144	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the read data pipeline 108 includes an output buffer 330 that receives requested packets from the alignment module 326 and stores the packets prior to transmission to the requesting device 155. The output buffer 330 accounts for differences between when data segments are received from stages of the read data pipeline 108 and when the data segments are transmitted to other parts of the solid-state storage controller 104 or to the requesting device 155. The output buffer 330 also allows the data bus 204 to receive data from the read data pipeline 108 at rates greater than can be sustained by the read data pipeline 108 in order to improve efficiency of operation of the data bus 204.	143	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the read data pipeline 108 includes a read synchronization buffer 328 that buffers one or more requested packets read from the solid-state storage media 110 prior to processing by the read data pipeline 108. The read synchronization buffer 328 is at the boundary between the solid-state storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences.	142	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The alignment module 326 re-formats the data as data segments of a data structure in a form compatible with a device requesting the data segment prior to forwarding the data segment to the next stage. Typically, as data is processed by the read data pipeline 108, the size of data segments or packets changes at various stages. The alignment module 326 uses received data to format the data into data segments suitable to be sent to the requesting device 155 and joined to form a response. For example, data from a portion of a first data packet may be combined with data from a portion of a second data packet. If a data segment is larger than a data requested by the requesting device 155, the alignment module 326 may discard the unwanted data.	141	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The read data pipeline 108 includes an alignment module 326 that receives data from the depacketizer 324 and removes unwanted data. In one embodiment, a read command sent to the solid-state storage media 110 retrieves a packet of data. A device requesting the data may not require all data within the retrieved packet and the alignment module 326 removes the unwanted data. If all data within a retrieved page is requested data, the alignment module 326 does not remove any data.	140	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The voltages for Vmin, Vmax, x, y, z may vary based on the manufacturer of the storage cells. Read voltages, for example, may range between −3.5 and 5.8 volts, or between another predefined range of voltages. Similarly, the order of binary state changes 11, 01, 00, and 10 relative to read voltage thresholds may vary based on the encoding type used, such as a Gray code encoding type, a binary code encoding type, or the like. One example encoding type is described below with regard to FIG. 6C. As described in greater detail with regard to FIG. 6C, although a single MLC storage cell stores multiple bits, bits from a single storage cell may not have adjacent addresses, and may be included in different physical pages, logical pages, or the like.	149	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet that cannot be corrected by the ECC decoder 322 is read by the master controller 224, corrected, and returned to the ECC decoder 322 for further processing by the read data pipeline 108. In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet is sent to the device requesting the data. The requesting device 155 may correct the ECC block or replace the data using another copy, such as a backup or mirror copy, and then may use the replacement data of the requested data packet or return it to the read data pipeline 108. The requesting device 155 may use header information in the requested packet in error to identify data required to replace the corrupted requested packet or to replace the data structure to which the packet belongs. In another embodiment, the solid-state storage controller 104 stores data using some type of RAID and is able to recover the corrupted data. In another embodiment, the ECC decoder 322 sends an interrupt and/or message and the receiving device fails the read operation associated with the requested data packet. One of skill in the art will recognize other options and actions to be taken as a result of the ECC decoder 322 determining that one or more ECC blocks of the requested packet are corrupted and that the ECC decoder 322 cannot correct the errors.	138	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	If the ECC decoder 322 determines that the requested packets contains more bits in error than the ECC can correct, the ECC decoder 322 cannot correct the errors in the corrupted ECC blocks of the requested packet and sends an interrupt. In one embodiment, the ECC decoder 322 sends an interrupt with a message indicating that the requested packet is in error. The message may include information that the ECC decoder 322 cannot correct the errors or the inability of the ECC decoder 322 to correct the errors may be implied. In another embodiment, the ECC decoder 322 sends the corrupted ECC blocks of the requested packet with the interrupt and/or the message.	137	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, the ECC decoder 322 may provide error information for correctable errors to the configuration module 352, described below, such as locations of the bits in error, values for the bits in error, and/or other error information. For example, the ECC decoder 322 may provide an error bias to the configuration module 352, indicating one or more bits of a data set that are in error, or the like. An error bias, as used herein, is a representation of one or more detected bit errors in a data set. In one embodiment, an error bias includes a location or position of a detected bit error in a data set. In another embodiment, an error bias includes a value for a detected bit error. A value for a detected error may include an error corrected value of a bit in error, an error value of the bit in error, or the like. For example, in one embodiment, the ECC decoder 322 may provide the configuration module 352 with an uncorrected data set and an error bias indicating locations of detected bit errors and the configuration module 352 may determine a known bias by inverting or flipping the bits in those locations. In another embodiment, for example, the ECC decoder 322 may provide the configuration module 352 with an error corrected data set and an error bias indicating locations of detected bit errors and the configuration module 352 may determine a read bias by inverting or flipping the bits in those locations.	136	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The read data pipeline 108 includes an ECC decoder 322 that determines if a data error exists in ECC blocks a requested packet received from the solid-state storage media 110 by using ECC stored with each ECC block of the requested packet. The ECC decoder 322 then corrects any errors in the requested packet if any error exists and the errors are correctable using the ECC. For example, if the ECC can detect an error in six bits but can only correct three bit errors, the ECC decoder 322 corrects ECC blocks of the requested packet with up to three bits in error. The ECC decoder 322 corrects the bits in error by changing the bits in error to the correct one or zero state so that the requested data packet is identical to when it was written to the solid-state storage media 110 and the ECC was generated for the packet.	135	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Read Data Pipeline	134	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Note that the write program module 310 is shown between the input buffer 306 and the compression module 312, however, the write program module 310 could be anywhere in the write data pipeline 106 and may be distributed among the various stages 302-320. In addition, there may be multiple write program modules 310 distributed among the various states 302-320 that are programmed and operate independently. In addition, the order of the stages 302-320 may be altered. One of skill in the art will recognize workable alterations to the order of the stages 302-320 based on particular user requirements.	133	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the write data pipeline 106 includes a write program module 310 with one or more user-definable functions within the write data pipeline 106. The write program module 310 allows a user to customize the write data pipeline 106. A user may customize the write data pipeline 106 based on a particular data requirement or application. Where the solid-state storage controller 104 is an FPGA, the user may program the write data pipeline 106 with custom commands and functions relatively easily. A user may also use the write program module 310 to include custom functions with an ASIC, however, customizing an ASIC may be more difficult than with an FPGA. The write program module 310 may include buffers and bypass mechanisms to allow a first data segment to execute in the write program module 310 while a second data segment may continue through the write data pipeline 106. In another embodiment, the write program module 310 may include a processor core that can be programmed through software.	132	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In another embodiment, the write buffer 320 is sized smaller than a virtual page so that less than a page of information could be written to a storage write buffer in the solid-state storage media 110. In the embodiment, to prevent a stall in the write data pipeline 106 from holding up read operations, data is queued using the garbage collection system that needs to be moved from one location to another as part of the garbage collection process. In case of a data stall in the write data pipeline 106, the data can be fed through the garbage collector bypass 316 to the write buffer 320 and then on to the storage write buffer in the solid-state storage media 110 to fill the pages of a virtual page prior to programming the data. In this way a data stall in the write data pipeline 106 would not stall reading from the solid-state storage device 102.	131	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the ECC encoder 304 creates independent ECC checkbits for each channel, storage element, die, chip, PEB, or other grouping of storage cells. The ECC checkbits are stored with the data on a particular grouping of storage cells rather than being distributed across multiple groupings. If ECC checkbits are created and stored independently for each grouping of storage cells, the configuration module 352, in response to a data error, may use the ECC checkbits and the known architecture for how an ECC checkbits are written to the groupings of storage cells to determine in which grouping of storage cells the data error occurred, and adjust the read voltage thresholds of those groupings. If ECC checkbits for the data packet are stored across multiple groupings of storage cells, the configuration module 352 may separately check the read biases of data sets from each grouping of storage cells and adjust one or more of the corresponding read voltage thresholds. An array of storage elements with multiple channels is described in greater detail with regard to FIGS. 6A and 6B.	158	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Configuring Storage Cells	167	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The solid-state storage controller 104 and or solid-state storage device 102 may also include a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350.	166	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Commands or instructions may be simultaneously loaded into the control queues 342 for a packet being forwarded to the write data pipeline 106 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage. Similarly, commands or instructions may be simultaneously loaded into the control queues 342 for a packet being requested from the read data pipeline 108 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage. One of skill in the art will recognize other features and functions of control and status registers 340 and control queues 342.	165	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The solid-state storage controller 104 includes control and status registers 340 and corresponding control queues 342. The control and status registers 340 and control queues 342 facilitate control and sequencing commands and subcommands associated with data processed in the write and read data pipelines 106, 108. For example, a data segment in the packetizer 302 may have one or more corresponding control commands or instructions in a control queue 342 associated with the ECC encoder 304. As the data segment is packetized, some of the instructions or commands may be executed within the packetizer 302. Other commands or instructions may be passed to the next control queue 342 through the control and status registers 340 as the newly formed data packet created from the data segment is passed to the next stage.	164	Added by DJM 3 2021	3/12/21, 12:00 AM

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