"Memory array" refers to a set of storage cells (also referred to as memory cells) organized into an array structure having rows and columns. A memory array is addressable using a row identifier and a column identifier. … more "Memory array" refers to a set of storage cells (also referred to as memory cells) organized into an array structure having rows and columns. A memory array is addressable using a row identifier and a column identifier.

"Host memory buffer" ("HMB") refers to volatile memory in a host allocated for use instead of, or in addition to, volatile memory in a non-volatile storage device for storing portions of an address mapping table. For example, some non-volatile storage devices may not have volatile memory, or may have a very small amount of available volatile memory and the HMB may serve the same, or similar, function as volatile memory in a non-volatile storage device.As another example, even if the non-volatile storage device includes volatile memory, a HMB may be used as a cache, a cache level, or a “spillover” memory for the address mapping table, so more entries of the address mapping table can be stored in volatile memory (i.e., in the volatile memory of the non-volatile storage device and the HMB of a host). This can improve performance, as storing more entries of the address mapping table can decrease the need to access the address mapping table in slower memory/storage such as non-volatile memory. … more "Host memory buffer" ("HMB") refers to volatile memory in a host allocated for use instead of, or in addition to, volatile memory in a non-volatile storage device for storing portions of an address mapping table. For example, some non-volatile storage devices may not have volatile memory, or may have a very small amount of available volatile memory and the HMB may serve the same, or similar, function as volatile memory in a non-volatile storage device.As another example, even if the non-volatile storage device includes volatile memory, a HMB may be used as a cache, a cache level, or a “spillover” memory for the address mapping table, so more entries of the address mapping table can be stored in volatile memory (i.e., in the volatile memory of the non-volatile storage device and the HMB of a host). This can improve performance, as storing more entries of the address mapping table can decrease the need to access the address mapping table in slower memory/storage such as non-volatile memory.

"Storage security firmware image" refers to a firmware image configured to manage, control and operate a security component or device designed, configured, or calibrated, to provide security for a storage device or component and/or monitor activity of a storage device to guard against a security breach or other security failure. … more "Storage security firmware image" refers to a firmware image configured to manage, control and operate a security component or device designed, configured, or calibrated, to provide security for a storage device or component and/or monitor activity of a storage device to guard against a security breach or other security failure.

"Reporter" refers to any hardware, firmware, software, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to report, notify, signal, alert or otherwise communicate a message to another circuit, component, module, device, or system. … more "Reporter" refers to any hardware, firmware, software, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to report, notify, signal, alert or otherwise communicate a message to another circuit, component, module, device, or system.

"Flash translation manager" refers to logic in a non-volatile storage device that includes logical-to-physical address translation providing abstraction of the logical block addresses used by the storage client and the physical block addresses at which the storage controller stores data. The logical-to-physical translation layer maps logical block addresses (LBAs) to physical addresses of data stored on solid-state storage media. In certain embodiments, the mapping is managed using an address mapping table. This mapping allows data to be referenced in a logical block address space using logical identifiers, such as a block address. A logical identifier does not indicate the physical location of data on the solid-state storage media but is an abstract reference to the data. … more "Flash translation manager" refers to logic in a non-volatile storage device that includes logical-to-physical address translation providing abstraction of the logical block addresses used by the storage client and the physical block addresses at which the storage controller stores data. The logical-to-physical translation layer maps logical block addresses (LBAs) to physical addresses of data stored on solid-state storage media. In certain embodiments, the mapping is managed using an address mapping table. This mapping allows data to be referenced in a logical block address space using logical identifiers, such as a block address. A logical identifier does not indicate the physical location of data on the solid-state storage media but is an abstract reference to the data.

"Initialization operation" refers to any operation, process, method, procedure, and/or sequence of steps that are performed, either in series or in parallel, in order to prepare a device, module, circuit, component, sub-system, or system to begin performing normal operations. … more "Initialization operation" refers to any operation, process, method, procedure, and/or sequence of steps that are performed, either in series or in parallel, in order to prepare a device, module, circuit, component, sub-system, or system to begin performing normal operations.

"Storage controller firmware image" refers to a firmware image configured to manage, control and operate a storage component or device. … more "Storage controller firmware image" refers to a firmware image configured to manage, control and operate a storage component or device.

"Anomaly detector" refers to a device, component, circuit, system, logic, chip, or circuitry configured to identify, mark, signal, log, or annotate an anomaly based on one or more of, a given set of input, historical data, and the like. … more "Anomaly detector" refers to a device, component, circuit, system, logic, chip, or circuitry configured to identify, mark, signal, log, or annotate an anomaly based on one or more of, a given set of input, historical data, and the like.

"Positive correlation" refers to a correlation in which two or more correlated things respond in the same manner to a particular influence, environment, action, or stimuli. For example, where threshold voltages of memory cells are represented by cell threshold voltage distributions and the cell threshold voltage distributions are mapped to memory states, memory cells within a first memory state are positively correlated to memory cells within a second memory state when the correlated attribute changes in the same direction for the memory cells of the first memory state and the memory cells of the second memory state. Said another way, if the correlated attribute increases for the memory cells of the first memory state and the correlated attribute increases for the memory cells of the second memory state, this is a positive correlation. In certain embodiments, the correlated attribute may comprise a threshold voltage, or change in a cell threshold voltage distribution for a set of memory cells in a memory state. … more "Positive correlation" refers to a correlation in which two or more correlated things respond in the same manner to a particular influence, environment, action, or stimuli. For example, where threshold voltages of memory cells are represented by cell threshold voltage distributions and the cell threshold voltage distributions are mapped to memory states, memory cells within a first memory state are positively correlated to memory cells within a second memory state when the correlated attribute changes in the same direction for the memory cells of the first memory state and the memory cells of the second memory state. Said another way, if the correlated attribute increases for the memory cells of the first memory state and the correlated attribute increases for the memory cells of the second memory state, this is a positive correlation. In certain embodiments, the correlated attribute may comprise a threshold voltage, or change in a cell threshold voltage distribution for a set of memory cells in a memory state.

"Width correlation" refers to a correlation in which memory cells of a cell threshold voltage distribution within a first memory state change threshold voltage in a manner that widens or narrows a curve representing the cell threshold voltage distribution within the first memory state in response to passage of time, or use of a storage device, in a manner that correlates to a change of threshold voltage in a manner that widens or narrows a curve representing the cell threshold voltage distribution within the second memory state. … more "Width correlation" refers to a correlation in which memory cells of a cell threshold voltage distribution within a first memory state change threshold voltage in a manner that widens or narrows a curve representing the cell threshold voltage distribution within the first memory state in response to passage of time, or use of a storage device, in a manner that correlates to a change of threshold voltage in a manner that widens or narrows a curve representing the cell threshold voltage distribution within the second memory state.

"Candidate read level" refers to a value, setting, configuration, numeric value, offset, or the like for a read level that may provide more accurate sensing of memory cells and/or reading of data from memory cells than a current read level. In certain embodiments, candidate read levels may be predetermined, and may be stored in a repository such as a data structure. In other embodiments, candidate read levels may be predetermined and may be organized into a predefined order which a read scan circuit may be configured to follow in selecting candidate read levels to use in determining a read level to replace a current read level.In still other embodiments, candidate read levels may be calculated based on results of one or more prior sense, and/or read operations (referred to herein as a “scan” or “scans”), that a read scan circuit may perform on a set of storage cells. For example, in one embodiment, the read scan circuit may compare results of a prior scan to results for a current scan using a current candidate read level. If the results with the current candidate read level are more favorable, the read scan circuit may calculate a next candidate read level based on the current candidate read level. If the results with the current candidate read level are less favorable, the read scan circuit may calculate a next candidate read level based on one or more prior scans using candidate read levels. In embodiments that determine which candidate read levels to use with successive iterations, a read scan circuit may apply a positive or negative offset to a current read level to determine a next candidate read level.A candidate read level may comprise one of a plurality of read levels positioned generally between a majority of memory cells of cell threshold voltage distributions for two adjacent memory states. It is desirable that candidate read levels result in optimal performance when reading data from memory cells programmed to one of the two adjacent memory states. In one embodiment, at least one of the candidate read levels will produce an optimal result, result in the fewest number of bit errors when reading from one of the adjacent memory states. Such candidate read levels may be referred to as a target read level. A target read level is a read level that results in a smallest or fewest number of activated memory cells in relation to other candidate read levels that may be iteratively checked. In another embodiment, the target read level is a read level that results in a smallest or fewest number of bit errors or bit error rate or estimated bit error rate from a read set of memory cells in relation to other candidate read levels that may be iteratively checked. … more "Candidate read level" refers to a value, setting, configuration, numeric value, offset, or the like for a read level that may provide more accurate sensing of memory cells and/or reading of data from memory cells than a current read level. In certain embodiments, candidate read levels may be predetermined, and may be stored in a repository such as a data structure. In other embodiments, candidate read levels may be predetermined and may be organized into a predefined order which a read scan circuit may be configured to follow in selecting candidate read levels to use in determining a read level to replace a current read level.In still other embodiments, candidate read levels may be calculated based on results of one or more prior sense, and/or read operations (referred to herein as a “scan” or “scans”), that a read scan circuit may perform on a set of storage cells. For example, in one embodiment, the read scan circuit may compare results of a prior scan to results for a current scan using a current candidate read level. If the results with the current candidate read level are more favorable, the read scan circuit may calculate a next candidate read level based on the current candidate read level. If the results with the current candidate read level are less favorable, the read scan circuit may calculate a next candidate read level based on one or more prior scans using candidate read levels. In embodiments that determine which candidate read levels to use with successive iterations, a read scan circuit may apply a positive or negative offset to a current read level to determine a next candidate read level.A candidate read level may comprise one of a plurality of read levels positioned generally between a majority of memory cells of cell threshold voltage distributions for two adjacent memory states. It is desirable that candidate read levels result in optimal performance when reading data from memory cells programmed to one of the two adjacent memory states. In one embodiment, at least one of the candidate read levels will produce an optimal result, result in the fewest number of bit errors when reading from one of the adjacent memory states. Such candidate read levels may be referred to as a target read level. A target read level is a read level that results in a smallest or fewest number of activated memory cells in relation to other candidate read levels that may be iteratively checked. In another embodiment, the target read level is a read level that results in a smallest or fewest number of bit errors or bit error rate or estimated bit error rate from a read set of memory cells in relation to other candidate read levels that may be iteratively checked.

"Stable correlation" refers to a correlation that comprises an accuracy rate and/or a set of historical testing or supporting data such that the correlation is true for a majority of instances in the future. … more "Stable correlation" refers to a correlation that comprises an accuracy rate and/or a set of historical testing or supporting data such that the correlation is true for a majority of instances in the future.

"Physical erase block" refers to smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die). … more "Physical erase block" refers to smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die).

"Logical page" refers to a collection of physical page that are treated as a single page for storage operations. … more "Logical page" refers to a collection of physical page that are treated as a single page for storage operations.

"Correlation data structure" refers to a data structure configured to store one or more correlation factors and an index for identifying the correlation factor for a particular correlation between two items or things. In one embodiment, a correlation data structure may be a table, an array, a list, a linked list, portion of a memory, a database, or the like. An index for the correlation data structure for correlation factors between memory states may comprise a row identifier for a memory state of correlation data structure table and a correlated memory state may comprise a column of the correlation data structure table. … more "Correlation data structure" refers to a data structure configured to store one or more correlation factors and an index for identifying the correlation factor for a particular correlation between two items or things. In one embodiment, a correlation data structure may be a table, an array, a list, a linked list, portion of a memory, a database, or the like. An index for the correlation data structure for correlation factors between memory states may comprise a row identifier for a memory state of correlation data structure table and a correlated memory state may comprise a column of the correlation data structure table.

"Correlation" refers to a relation existing between phenomena, attributes, behaviors, or things or between mathematical or statistical variables which tend to vary, be associated, or occur together in a way not expected on the basis of chance alone. (“Correlation.” Merriam-Webster.com Dictionary, Merriam-Webster, Accessed 10 Apr. 2020. Edited.) A relation/correlation may be represented in a variety of ways, including by use of numbers, formulas, graphs, diagrams or the like. In certain embodiments, the correlation may represent a one-way relationship between a first thing and a second thing, meaning the correlation exists from the first thing to the second thing but not from the second thing to the first thing. In other embodiments, the correlation may represent a two-way relationship between a first thing and a second thing, meaning that the same correlation exists in comparing the first thing to the second thing and from the second thing to the first thing.In certain embodiments, the correlation represents a magnitude and/or rate of change in an attribute or behavior between two or more things. Correlations may be observed, or derived, by testing and analysis of results from normal use, experiments, machine learning, or the like. Correlations between two things, such as memory cells, threshold voltages, memory die, memory states, cell threshold voltage distributions, or the like, may be characterized as positive correlations or negative correlations. … more "Correlation" refers to a relation existing between phenomena, attributes, behaviors, or things or between mathematical or statistical variables which tend to vary, be associated, or occur together in a way not expected on the basis of chance alone. (“Correlation.” Merriam-Webster.com Dictionary, Merriam-Webster, Accessed 10 Apr. 2020. Edited.) A relation/correlation may be represented in a variety of ways, including by use of numbers, formulas, graphs, diagrams or the like. In certain embodiments, the correlation may represent a one-way relationship between a first thing and a second thing, meaning the correlation exists from the first thing to the second thing but not from the second thing to the first thing. In other embodiments, the correlation may represent a two-way relationship between a first thing and a second thing, meaning that the same correlation exists in comparing the first thing to the second thing and from the second thing to the first thing.In certain embodiments, the correlation represents a magnitude and/or rate of change in an attribute or behavior between two or more things. Correlations may be observed, or derived, by testing and analysis of results from normal use, experiments, machine learning, or the like. Correlations between two things, such as memory cells, threshold voltages, memory die, memory states, cell threshold voltage distributions, or the like, may be characterized as positive correlations or negative correlations.

"Read scan operation" refers to a maintenance operation performed to identify and mitigate or avoid or counter errors in the data or storage cells and/or other components of a non-volatile storage device. A read scan operation may be referred to, interchangeably, as a "read scan" or “read scan operation.” In one embodiment, a read scan operation involves reading data from, or sensing a determinable physical characteristic, or a memory state of storage cells in a storage block. Next, the read scan operation checks the memory states of the storage cells for any errors, corrects as many errors as possible, and determines a bit error rate. Then, the read scan operation determines if the bit error rate satisfies a threshold such as a read bit error rate threshold.In one embodiment, the read scan operation reads data from each logical page, or word line, of the storage block. In another embodiment, the read scan operation selects less than all of the logical pages of the storage block. In other words, the read scan operation may sample the logical pages of the storage block from which to read data for the read scan operation.If a read bit error rate threshold is satisfied, the read scan operation then may perform a data scrub operation or a data refresh operation. In certain embodiments, a read scan operation may always include a data scrub operation or a data refresh operation. In other embodiments, performing a data scrub operation or data refresh operation may be conditioned on the bit error rate satisfying a read bit error rate threshold. In such embodiments, a read scan operation may be referred to as a “read scrub” or "read scrub operation." In these embodiments, a read scan operation may conditionally include a data scrub operation.In certain embodiments, a read scan operation may operate as a foreground process meaning that the read scan operation interrupts, or delays, a non-volatile storage device from servicing read commands or write commands for a host. In addition, the read scan operation may need to complete working on a particular storage block and thereby delay a host read command for data on that particular storage block. Thus, in such embodiments, a read scan operation may impact quality of service levels between a host and the non-volatile storage device. … more "Read scan operation" refers to a maintenance operation performed to identify and mitigate or avoid or counter errors in the data or storage cells and/or other components of a non-volatile storage device. A read scan operation may be referred to, interchangeably, as a "read scan" or “read scan operation.” In one embodiment, a read scan operation involves reading data from, or sensing a determinable physical characteristic, or a memory state of storage cells in a storage block. Next, the read scan operation checks the memory states of the storage cells for any errors, corrects as many errors as possible, and determines a bit error rate. Then, the read scan operation determines if the bit error rate satisfies a threshold such as a read bit error rate threshold.In one embodiment, the read scan operation reads data from each logical page, or word line, of the storage block. In another embodiment, the read scan operation selects less than all of the logical pages of the storage block. In other words, the read scan operation may sample the logical pages of the storage block from which to read data for the read scan operation.If a read bit error rate threshold is satisfied, the read scan operation then may perform a data scrub operation or a data refresh operation. In certain embodiments, a read scan operation may always include a data scrub operation or a data refresh operation. In other embodiments, performing a data scrub operation or data refresh operation may be conditioned on the bit error rate satisfying a read bit error rate threshold. In such embodiments, a read scan operation may be referred to as a “read scrub” or "read scrub operation." In these embodiments, a read scan operation may conditionally include a data scrub operation.In certain embodiments, a read scan operation may operate as a foreground process meaning that the read scan operation interrupts, or delays, a non-volatile storage device from servicing read commands or write commands for a host. In addition, the read scan operation may need to complete working on a particular storage block and thereby delay a host read command for data on that particular storage block. Thus, in such embodiments, a read scan operation may impact quality of service levels between a host and the non-volatile storage device.

"Memory state" refers to a condition, attribute, and/or characteristic, of a memory cell, or storage cell, designed and/or configured to represent an encoding for one or more data bit values. In certain embodiments, the memory state may be changed by way of a storage operation. In a non-volatile memory cell, the memory cell maintains its memory state without a power source.In certain embodiments, and in certain contexts, memory state may also refer to a collection, or set of memory cells, that collectively have a similar condition, attribute, and/or characteristic. In relation to non-volatile memory cells, groups, collections, or sets of memory cells with a similar condition within a certain range may be referred to collectively as memory cells of a particular memory state. Furthermore, reference may be made to a memory state as a shorthand reference to all memory cells having a condition that falls within a predefined range defined for that memory state.For example, with NAND memory cells, a threshold voltage (Vt) window may be defined between a negative threshold voltage, or approximately zero threshold voltage, and a maximum threshold voltage. Within this Vt window, a number of sub-ranges may be defined and referred to as memory states. In certain embodiments, the whole Vt window may be divided up such that each threshold voltage falls within one of the memory states. In one embodiment, each memory state has a lower boundary and an upper boundary and may be represented by a cell threshold voltage distribution. … more "Memory state" refers to a condition, attribute, and/or characteristic, of a memory cell, or storage cell, designed and/or configured to represent an encoding for one or more data bit values. In certain embodiments, the memory state may be changed by way of a storage operation. In a non-volatile memory cell, the memory cell maintains its memory state without a power source.In certain embodiments, and in certain contexts, memory state may also refer to a collection, or set of memory cells, that collectively have a similar condition, attribute, and/or characteristic. In relation to non-volatile memory cells, groups, collections, or sets of memory cells with a similar condition within a certain range may be referred to collectively as memory cells of a particular memory state. Furthermore, reference may be made to a memory state as a shorthand reference to all memory cells having a condition that falls within a predefined range defined for that memory state.For example, with NAND memory cells, a threshold voltage (Vt) window may be defined between a negative threshold voltage, or approximately zero threshold voltage, and a maximum threshold voltage. Within this Vt window, a number of sub-ranges may be defined and referred to as memory states. In certain embodiments, the whole Vt window may be divided up such that each threshold voltage falls within one of the memory states. In one embodiment, each memory state has a lower boundary and an upper boundary and may be represented by a cell threshold voltage distribution.

"Predefined order" refers to a sequence of steps, operations, selections, functions, determination, or actions in an order that is defined before an operation that follows the predefined order is initiated. … more "Predefined order" refers to a sequence of steps, operations, selections, functions, determination, or actions in an order that is defined before an operation that follows the predefined order is initiated.

"Logical erase block" refers to another term for a storage block. In certain embodiments, a logical erase block refers to a set of logical pages that span planes, memory die, and/or chips. This organization of storage cells is deemed 'logical' because the physical pages may not be directly coupled to each other. However, the physical pages are operated in parallel as though they are a single page. In like manner, multiple physical erase blocks may be operated in parallel as though they are a single erase block and are thus referred to as logical erase blocks. The terms logical erase block, metablock, and super block are used interchangeably herein. … more "Logical erase block" refers to another term for a storage block. In certain embodiments, a logical erase block refers to a set of logical pages that span planes, memory die, and/or chips. This organization of storage cells is deemed 'logical' because the physical pages may not be directly coupled to each other. However, the physical pages are operated in parallel as though they are a single page. In like manner, multiple physical erase blocks may be operated in parallel as though they are a single erase block and are thus referred to as logical erase blocks. The terms logical erase block, metablock, and super block are used interchangeably herein.