"First gate node" refers to a node of an electronic circuit that connects to a gate terminal of a first NMOS transistor in a cascoded configuration connected between a second NMOS transistor and an IO pad. … more "First gate node" refers to a node of an electronic circuit that connects to a gate terminal of a first NMOS transistor in a cascoded configuration connected between a second NMOS transistor and an IO pad.

"Strobe signal" refers to a digital electric signal applied to a control line by a driver and configured to raise a voltage and/or current of the control line. In certain embodiments, a strobe signal is configured to oscillate between an elevated level and a non-elevated level, and the oscillation occurs over a regular period defined as cycles. Such oscillating strobe signals may serve as a clock, or clock signal, for transferring data in a digital circuit. … more "Strobe signal" refers to a digital electric signal applied to a control line by a driver and configured to raise a voltage and/or current of the control line. In certain embodiments, a strobe signal is configured to oscillate between an elevated level and a non-elevated level, and the oscillation occurs over a regular period defined as cycles. Such oscillating strobe signals may serve as a clock, or clock signal, for transferring data in a digital circuit.

"Supply voltage" refers to a source for a voltage level used to operate an electrical circuit during normal operation. … more "Supply voltage" refers to a source for a voltage level used to operate an electrical circuit during normal operation.

"Triggering voltage" refers to a voltage level which, when experienced on a node or signal line within a circuit, causes an action to be taken by that circuit. The action may be to turn additional signals on or off, power an indicator or alarm, open a power connection, etc., in response to the triggering voltage being sensed. … more "Triggering voltage" refers to a voltage level which, when experienced on a node or signal line within a circuit, causes an action to be taken by that circuit. The action may be to turn additional signals on or off, power an indicator or alarm, open a power connection, etc., in response to the triggering voltage being sensed.

"Pad bias circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured to bias an IO pad during an ESD event. … more "Pad bias circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured to bias an IO pad during an ESD event.

"Reference voltage node" refers to a node of an electronic circuit that serves as a derived voltage in relation to a voltage level at an IO pad. A voltage level of a reference voltage node may be compared within a snapback ESD circuit to a supply voltage and/or to a voltage level at an IO pad. … more "Reference voltage node" refers to a node of an electronic circuit that serves as a derived voltage in relation to a voltage level at an IO pad. A voltage level of a reference voltage node may be compared within a snapback ESD circuit to a supply voltage and/or to a voltage level at an IO pad.

"Trigger circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured to activate an ESD protection circuit in response to detecting an ESD event. … more "Trigger circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured to activate an ESD protection circuit in response to detecting an ESD event.

"Gate bias circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured to bias gate terminals of two or more transistors of an ESD protection circuit in a cascoded configuration. … more "Gate bias circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured to bias gate terminals of two or more transistors of an ESD protection circuit in a cascoded configuration.