"Read level" refers to a voltage level configured to test, check, read, or sense, which memory cells conduct at the voltage level. In certain embodiments, the memory cells may comprise transistors and the read level, or read voltage, is a voltage level at, or above a threshold voltage for the memory cells which causes the memory cell to conduct a current, to activate.In certain embodiments, depending on the type of encoding used to store data on the memory cell and the number of bits encoded on each memory cell, a single read/sense operation using a single read voltage may be determinative of the memory state of the memory cell. In other embodiments, a number of read/sense operations each performed at different read voltage levels may be used to determine the memory state of the memory cell. The determined memory state may then be decoded into a representation of the data bits stored by the memory cell. "Read voltage" is a shorthand reference to a "read threshold voltage." "Read level" is another term commonly used to describe a "read voltage" and the two terms are used interchangeably herein. … more "Read level" refers to a voltage level configured to test, check, read, or sense, which memory cells conduct at the voltage level. In certain embodiments, the memory cells may comprise transistors and the read level, or read voltage, is a voltage level at, or above a threshold voltage for the memory cells which causes the memory cell to conduct a current, to activate.In certain embodiments, depending on the type of encoding used to store data on the memory cell and the number of bits encoded on each memory cell, a single read/sense operation using a single read voltage may be determinative of the memory state of the memory cell. In other embodiments, a number of read/sense operations each performed at different read voltage levels may be used to determine the memory state of the memory cell. The determined memory state may then be decoded into a representation of the data bits stored by the memory cell. "Read voltage" is a shorthand reference to a "read threshold voltage." "Read level" is another term commonly used to describe a "read voltage" and the two terms are used interchangeably herein.

"Correlation factor" refers to a value that modifies a correlated attribute when the correlated attribute is multiplied by the correlation factor such that the correlated attribute accounts for a correlation associated with the correlation factor. For example, in one embodiment, the correlated attribute may be a read level. Each read level may mark a boundary between two adjacent memory states. A correlation factor may represent how one memory state relates to another memory state such that multiplying the correlation factor by a current read level results in a correlated read level modified to account for the correlation. A correlation factor may be a real number and may be a positive number reflecting a positive correlation, a negative number reflecting a negative correlation, a zero representing no correlation, or a 1 representing a complete correlation. … more "Correlation factor" refers to a value that modifies a correlated attribute when the correlated attribute is multiplied by the correlation factor such that the correlated attribute accounts for a correlation associated with the correlation factor. For example, in one embodiment, the correlated attribute may be a read level. Each read level may mark a boundary between two adjacent memory states. A correlation factor may represent how one memory state relates to another memory state such that multiplying the correlation factor by a current read level results in a correlated read level modified to account for the correlation. A correlation factor may be a real number and may be a positive number reflecting a positive correlation, a negative number reflecting a negative correlation, a zero representing no correlation, or a 1 representing a complete correlation.

"Read operation" refers to an operation performed on a memory cell in order to obtain, sense, detect, or determine a value for data represented by a state characteristic of the memory cell. … more "Read operation" refers to an operation performed on a memory cell in order to obtain, sense, detect, or determine a value for data represented by a state characteristic of the memory cell.

"Storage operation" refers to an operation performed on a memory cell in order to change, or obtain, the value of data represented by a state characteristic of the memory cell. Examples of storage operations include but are not limited to reading data from (or sensing a state of) a memory cell, writing (or programming) data to a memory cell, and/or erasing data stored in a memory cell. … more "Storage operation" refers to an operation performed on a memory cell in order to change, or obtain, the value of data represented by a state characteristic of the memory cell. Examples of storage operations include but are not limited to reading data from (or sensing a state of) a memory cell, writing (or programming) data to a memory cell, and/or erasing data stored in a memory cell.

"Storage cell" refers to a type of storage media configured to represent one or more binary values by way of a determinable characteristic of the storage media when the storage media is sensed, read, or detected to determine a binary value(s) stored, or represented by, the determinable characteristic of the memory cell. Storage cell and memory cell are used interchangeably herein.The type of determinable characteristic used to store data in a memory cell may vary depending on the type of memory or storage technology used. For example, in flash memory cells in which each memory cell comprises a transistor having a source lead, a drain lead and a gate, the determinable characteristic is a voltage level that when applied to the gate causes the memory cell to conduct a current between the drain and the source leads. The voltage level, in this example, is referred to herein as a threshold voltage. A threshold voltage may also be referred to as a control gate reference voltage (CGRV), read voltage, or reference voltage.Examples of the determinable physical characteristic include, but are not limited to, a threshold voltage for a transistor, an electrical resistance level of a memory cell, a current level through a memory cell, a magnetic pole orientation, a spin-transfer torque, and the like. … more "Storage cell" refers to a type of storage media configured to represent one or more binary values by way of a determinable characteristic of the storage media when the storage media is sensed, read, or detected to determine a binary value(s) stored, or represented by, the determinable characteristic of the memory cell. Storage cell and memory cell are used interchangeably herein.The type of determinable characteristic used to store data in a memory cell may vary depending on the type of memory or storage technology used. For example, in flash memory cells in which each memory cell comprises a transistor having a source lead, a drain lead and a gate, the determinable characteristic is a voltage level that when applied to the gate causes the memory cell to conduct a current between the drain and the source leads. The voltage level, in this example, is referred to herein as a threshold voltage. A threshold voltage may also be referred to as a control gate reference voltage (CGRV), read voltage, or reference voltage.Examples of the determinable physical characteristic include, but are not limited to, a threshold voltage for a transistor, an electrical resistance level of a memory cell, a current level through a memory cell, a magnetic pole orientation, a spin-transfer torque, and the like.

"Read scan circuit" refers to any circuit, sub-circuit, electronic component, hardware, software, firmware, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to execute a read scan operation. … more "Read scan circuit" refers to any circuit, sub-circuit, electronic component, hardware, software, firmware, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to execute a read scan operation.

"Configuration parameter" refers to a parameter of a set of storage cells that is modifiable by way of an interface, such as a read threshold, a write or program threshold, an erase threshold, or the like. An interface for modifying a configuration parameter may include a programmable data register, a command interface of a control bus for the non-volatile memory array, an API of a device driver of the storage device, a control parameter for the storage controller, or the like. … more "Configuration parameter" refers to a parameter of a set of storage cells that is modifiable by way of an interface, such as a read threshold, a write or program threshold, an erase threshold, or the like. An interface for modifying a configuration parameter may include a programmable data register, a command interface of a control bus for the non-volatile memory array, an API of a device driver of the storage device, a control parameter for the storage controller, or the like.

"Storage block" refers to a set of storage cells organized such that storage operations can be performed on groups of storage cells in parallel. The organization of the set of storage cells may be implemented at a physical level or a logical level. Thus, a storage block, in one embodiment, may comprise a physical page, such as a word line, a logical page comprising physical pages that span planes and/or memory die, a physical erase block comprising a set of physical pages, a logical erase block (LEB) comprising a set of logical pages, or the like. A storage block may be referred to herein as a “block”, a “memory block” or an LEB. … more "Storage block" refers to a set of storage cells organized such that storage operations can be performed on groups of storage cells in parallel. The organization of the set of storage cells may be implemented at a physical level or a logical level. Thus, a storage block, in one embodiment, may comprise a physical page, such as a word line, a logical page comprising physical pages that span planes and/or memory die, a physical erase block comprising a set of physical pages, a logical erase block (LEB) comprising a set of logical pages, or the like. A storage block may be referred to herein as a “block”, a “memory block” or an LEB.

"Adjacent memory state" refers to a memory state that neighbors a given memory state along a range of threshold voltages with no memory states defined between the given memory state and the adjacent memory state. … more "Adjacent memory state" refers to a memory state that neighbors a given memory state along a range of threshold voltages with no memory states defined between the given memory state and the adjacent memory state.

"Estimated bit error rate" refers to a value that directly, indirectly, and/or approximately represents a bit error rate for a certain set of data bits stored in one or more memory cells. Advantageously, an estimated bit error rate serves as a suitable proxy for a calculated bit error rate and may be obtained with fewer computing cycles and in a faster time than time needed to determine a bit error rate. One example of an estimated bit error rate is a rate resulting from a Bit Error Rate (BER) Estimation Scan (BES) operation. A BES read scan operation is a type of read scan operation in with candidate read levels for certain read levels for a logical page a tested in a predefined order. In one embodiment, the BES read scan operation tests a particular candidate read level and an algorithm determines results for simulated / emulated testing of other read levels for a particular logical page.A BES read scan operation, in one embodiment, may determine an estimated bit error rate by comparing syndrome weights between iterative read level sensing or read operations to determine which candidate read level results in the fewest number of activated memory cells. In such embodiments, a syndrome weight below a threshold serves as a proxy for a bit error rate, an estimated bit error rate. A syndrome weight is a number of unsatisfied ECC parity check equations nodes/equations from a Low-Density Parity-Check (LDPC) error correction code decoder (ECC decoder). … more "Estimated bit error rate" refers to a value that directly, indirectly, and/or approximately represents a bit error rate for a certain set of data bits stored in one or more memory cells. Advantageously, an estimated bit error rate serves as a suitable proxy for a calculated bit error rate and may be obtained with fewer computing cycles and in a faster time than time needed to determine a bit error rate. One example of an estimated bit error rate is a rate resulting from a Bit Error Rate (BER) Estimation Scan (BES) operation. A BES read scan operation is a type of read scan operation in with candidate read levels for certain read levels for a logical page a tested in a predefined order. In one embodiment, the BES read scan operation tests a particular candidate read level and an algorithm determines results for simulated / emulated testing of other read levels for a particular logical page.A BES read scan operation, in one embodiment, may determine an estimated bit error rate by comparing syndrome weights between iterative read level sensing or read operations to determine which candidate read level results in the fewest number of activated memory cells. In such embodiments, a syndrome weight below a threshold serves as a proxy for a bit error rate, an estimated bit error rate. A syndrome weight is a number of unsatisfied ECC parity check equations nodes/equations from a Low-Density Parity-Check (LDPC) error correction code decoder (ECC decoder).

"Read/write circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured and/or operational to read data from and write data to a storage media, such as storage cells of a storage array. … more "Read/write circuit" refers to a device, component, element, module, system, sub-system, circuitry, logic, hardware, or circuit configured and/or operational to read data from and write data to a storage media, such as storage cells of a storage array.

"Error correction code decoder" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to detect and/or correct errors in a data set using redundancy information defined for the data set (e.g., a code word).The error correction code decoder, in one embodiment, may comprise one or more types of decoder, including, but not limited to, a low density parity check (LDPC) decoder, a Reed-Solomon code decoder, a Golay code decoder, a Bose Chaudhuri Hocquenghem (BCH) code decoder, a turbo code decoder, a multidimensional parity code decoder, a Hamming code decoder, a Hadamard code decoder, an expander code decoder, a Reed-Muller code decoder, a Viterbi decoder, a Fano decoder, or the like. … more "Error correction code decoder" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to detect and/or correct errors in a data set using redundancy information defined for the data set (e.g., a code word).The error correction code decoder, in one embodiment, may comprise one or more types of decoder, including, but not limited to, a low density parity check (LDPC) decoder, a Reed-Solomon code decoder, a Golay code decoder, a Bose Chaudhuri Hocquenghem (BCH) code decoder, a turbo code decoder, a multidimensional parity code decoder, a Hamming code decoder, a Hadamard code decoder, an expander code decoder, a Reed-Muller code decoder, a Viterbi decoder, a Fano decoder, or the like.

"Alert threshold" refers to a type of threshold that is predefined such that when a value, rating, or condition satisfies the alert threshold, the system, apparatus, or method is configured to signal either a problem or error or a potential for an imminent problem or error condition. … more "Alert threshold" refers to a type of threshold that is predefined such that when a value, rating, or condition satisfies the alert threshold, the system, apparatus, or method is configured to signal either a problem or error or a potential for an imminent problem or error condition.

"Valley search operation" refers to is a type of read scan operation configured to iteratively test or check a number of candidate read levels around a boundary for a set of memory cells within cell threshold voltage distributions for two adjacent memory states. In certain embodiments, the valley search operation may begin with a current read level or a default read level which may have been set when a storage device is manufactured. Next the valley search operation may apply a candidate read level to determine if the candidate read level resulted in fewer memory cells activating than the current read level. If so, this means that more memory cells will be identified as being programmed to a correct memory state. If not, this means that more memory cells will be erroneously identified as being to one of the adjacent memory states. The valley search operation continues to iterate in this manner changing the candidate read level with each iteration until a read level is identified that results in the fewest number set of memory cells being activated and/or a fewest number of read errors (e.g., lower bit error rate). … more "Valley search operation" refers to is a type of read scan operation configured to iteratively test or check a number of candidate read levels around a boundary for a set of memory cells within cell threshold voltage distributions for two adjacent memory states. In certain embodiments, the valley search operation may begin with a current read level or a default read level which may have been set when a storage device is manufactured. Next the valley search operation may apply a candidate read level to determine if the candidate read level resulted in fewer memory cells activating than the current read level. If so, this means that more memory cells will be identified as being programmed to a correct memory state. If not, this means that more memory cells will be erroneously identified as being to one of the adjacent memory states. The valley search operation continues to iterate in this manner changing the candidate read level with each iteration until a read level is identified that results in the fewest number set of memory cells being activated and/or a fewest number of read errors (e.g., lower bit error rate).

"Cell threshold voltage distribution" refers to a process or method for determining a threshold voltage for each memory cell in a set of memory cells. Cell threshold voltage distribution may be referred to as cell voltage distribution and may be referred to using the acronym “CVD.”A cell threshold voltage distribution may be determined during research and development of non-volatile memory technology to understand how memory cells behave under different conditions. In certain embodiments, a cell threshold voltage distribution may be performed during operation of non-volatile memory to determine whether the read levels being used to read a memory cell are adequate. If a bit error rate for a first set of read levels is inadequate, countermeasures may be taken to reduce the bit error rate.In certain embodiment, these countermeasures may include adjusting configuration parameters such that a bit error rate decreases. In certain embodiments, the steps of determining a cell threshold voltage distribution, checking read levels and other media characteristics with respect to bit error rate, and taking any countermeasures, may be referred to as a CVD scan, a read scan, or a read scan operation. A CVD scan may require significant time to complete due to the various steps involved and the number of memory cells being scanned. In particular, where memory cells store four or more bits per memory cell, a CVD scan may incur high latency, unless aspects of the claimed solution are used. … more "Cell threshold voltage distribution" refers to a process or method for determining a threshold voltage for each memory cell in a set of memory cells. Cell threshold voltage distribution may be referred to as cell voltage distribution and may be referred to using the acronym “CVD.”A cell threshold voltage distribution may be determined during research and development of non-volatile memory technology to understand how memory cells behave under different conditions. In certain embodiments, a cell threshold voltage distribution may be performed during operation of non-volatile memory to determine whether the read levels being used to read a memory cell are adequate. If a bit error rate for a first set of read levels is inadequate, countermeasures may be taken to reduce the bit error rate.In certain embodiment, these countermeasures may include adjusting configuration parameters such that a bit error rate decreases. In certain embodiments, the steps of determining a cell threshold voltage distribution, checking read levels and other media characteristics with respect to bit error rate, and taking any countermeasures, may be referred to as a CVD scan, a read scan, or a read scan operation. A CVD scan may require significant time to complete due to the various steps involved and the number of memory cells being scanned. In particular, where memory cells store four or more bits per memory cell, a CVD scan may incur high latency, unless aspects of the claimed solution are used.

"Current read level" refers to a read level that is a value that is presently being used by a die controller or storage controller for read operations on memory cells. In certain embodiments, a current read level may be a default read level that has been used for prior read operations. In another embodiment, the current read level may comprise a read level set by a prior read scan operation and which may be changed in a presently executing read scan operation. … more "Current read level" refers to a read level that is a value that is presently being used by a die controller or storage controller for read operations on memory cells. In certain embodiments, a current read level may be a default read level that has been used for prior read operations. In another embodiment, the current read level may comprise a read level set by a prior read scan operation and which may be changed in a presently executing read scan operation.

"Plane" refers to a division of a die that permits certain storage operations to be performed on both planes using certain physical row addresses and certain physical column addresses. … more "Plane" refers to a division of a die that permits certain storage operations to be performed on both planes using certain physical row addresses and certain physical column addresses.

"Health manager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to review, test, check, configure, adjust, and/or adapt configuration parameters for memory cells, a memory die, and/or a storage controller so as to prolong the usefulness, effectiveness, and/or efficiency of a storage device. … more "Health manager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to review, test, check, configure, adjust, and/or adapt configuration parameters for memory cells, a memory die, and/or a storage controller so as to prolong the usefulness, effectiveness, and/or efficiency of a storage device.

"Bit error rate" refers to a measure of a number of bits in error of a total overall number of bits processed. Depending on the use case, a bit error rate may be calculated either before, or after, an Error Correction Code (ECC) decoder has made one or more attempts to correct one or more bits in error. … more "Bit error rate" refers to a measure of a number of bits in error of a total overall number of bits processed. Depending on the use case, a bit error rate may be calculated either before, or after, an Error Correction Code (ECC) decoder has made one or more attempts to correct one or more bits in error.

"Negative correlation" refers to a correlation in which two or more correlated things respond in an opposite manner to a particular influence, environment, action, or stimuli. For example, where threshold voltages of memory cells are represented by cell threshold voltage distributions and the cell threshold voltage distributions are mapped to memory states, memory cells within a first memory state are negatively correlated to memory cells within a second memory state when the correlated attribute changes in the opposite direction for the memory cells of the first memory state and the memory cells of the second memory state. Said another way, if the correlated attribute increases for the memory cells of the first memory state and the correlated attribute decreases for the memory cells of the second memory state, this is a negative correlation. In certain embodiments, the correlated attribute may comprise a threshold voltage, or change in a cell threshold voltage distribution for a set of memory cells in memory states. … more "Negative correlation" refers to a correlation in which two or more correlated things respond in an opposite manner to a particular influence, environment, action, or stimuli. For example, where threshold voltages of memory cells are represented by cell threshold voltage distributions and the cell threshold voltage distributions are mapped to memory states, memory cells within a first memory state are negatively correlated to memory cells within a second memory state when the correlated attribute changes in the opposite direction for the memory cells of the first memory state and the memory cells of the second memory state. Said another way, if the correlated attribute increases for the memory cells of the first memory state and the correlated attribute decreases for the memory cells of the second memory state, this is a negative correlation. In certain embodiments, the correlated attribute may comprise a threshold voltage, or change in a cell threshold voltage distribution for a set of memory cells in memory states.