"Stop event" refers to an event designated to indicate a suitable stopping point for a time measurement for the execution of a storage operation. … more "Stop event" refers to an event designated to indicate a suitable stopping point for a time measurement for the execution of a storage operation.

"Host memory buffer manager" refers to any hardware, firmware, software, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to manage and operation one or more host memory buffers. … more "Host memory buffer manager" refers to any hardware, firmware, software, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to manage and operation one or more host memory buffers.

"Latency" refers to a period of time, often characterized as a delay, between when an operation starts and when the operation stops, completes, or encounters an error condition. Latency may be measured in units of time such as nanoseconds, microseconds, milliseconds, seconds, minutes, hours, days, weeks, or the like. … more "Latency" refers to a period of time, often characterized as a delay, between when an operation starts and when the operation stops, completes, or encounters an error condition. Latency may be measured in units of time such as nanoseconds, microseconds, milliseconds, seconds, minutes, hours, days, weeks, or the like.

"Detector" refers to any hardware, software, firmware, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to analyze, examine, and/or review signal traffic or other operations and detect events that are associated with, or indicative of, a storage operation. … more "Detector" refers to any hardware, software, firmware, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to analyze, examine, and/or review signal traffic or other operations and detect events that are associated with, or indicative of, a storage operation.

"Storage processor" refers to a processor configured to manage and control storage operations on, among or between non-volatile storage devices and/or electronic components. In certain embodiments, a storage processor may be referred to as a central processing unit (CPU), an ASIC, a controller, a core, a physical core, or the like. … more "Storage processor" refers to a processor configured to manage and control storage operations on, among or between non-volatile storage devices and/or electronic components. In certain embodiments, a storage processor may be referred to as a central processing unit (CPU), an ASIC, a controller, a core, a physical core, or the like.

"Unpredictable storage operation" refers to a storage operation that completes within an undefined and unpredictable and not a semi-predictable time interval. Examples of an unpredictable storage operation may include certain maintenance storage operations. … more "Unpredictable storage operation" refers to a storage operation that completes within an undefined and unpredictable and not a semi-predictable time interval. Examples of an unpredictable storage operation may include certain maintenance storage operations.

"Internal communication bus" refers to a communication bus that connects or couples to a device or component at points within a device, housing or compartment that includes the device or component. In certain embodiments, an internal communication bus comprises a local interconnect, including a point to point interconnect, between two or more electronic components and may be implemented within a printed circuit board. Examples of an internal communication bus and/or associated protocols include, but are not limited to an Advanced eXtensible Interface (AXI), an ARM Advanced Microcontroller Bus Architecture (AMBA), a System Management Bus (SMBus, SMB), Inter-integrated Circuit (I2C), GENz, I3C, Peripheral Component Interconnect Express (PCIe) bus, and the like.In one embodiment, the internal communication bus may comprise a single bus or a combination of two or more busses. For example, in one embodiment, the internal communication bus may comprise a central bus (e.g., an Advanced Microcontroller Bus Architecture (“AMBA”) High-performance Bus (“AHB”) multi-layer matrix bus for the data path and an advanced peripheral bus (“APB”) for the command path. … more "Internal communication bus" refers to a communication bus that connects or couples to a device or component at points within a device, housing or compartment that includes the device or component. In certain embodiments, an internal communication bus comprises a local interconnect, including a point to point interconnect, between two or more electronic components and may be implemented within a printed circuit board. Examples of an internal communication bus and/or associated protocols include, but are not limited to an Advanced eXtensible Interface (AXI), an ARM Advanced Microcontroller Bus Architecture (AMBA), a System Management Bus (SMBus, SMB), Inter-integrated Circuit (I2C), GENz, I3C, Peripheral Component Interconnect Express (PCIe) bus, and the like.In one embodiment, the internal communication bus may comprise a single bus or a combination of two or more busses. For example, in one embodiment, the internal communication bus may comprise a central bus (e.g., an Advanced Microcontroller Bus Architecture (“AMBA”) High-performance Bus (“AHB”) multi-layer matrix bus for the data path and an advanced peripheral bus (“APB”) for the command path.

"Address mapping table" refers to a data structure that associates logical block addresses with physical addresses of data stored on a non-volatile memory array. Alternatively, or in addition, the address mapping table may be referred to as a logical-to-physical address map.The table may be implemented as an index, a map, a b-tree, a content addressable memory (CAM), a binary tree, a hash table, and the like. The address mapping table may be referred to interchangeably as a Group Allocation Table (GAT), logical-to-physical address map, or the like. … more "Address mapping table" refers to a data structure that associates logical block addresses with physical addresses of data stored on a non-volatile memory array. Alternatively, or in addition, the address mapping table may be referred to as a logical-to-physical address map.The table may be implemented as an index, a map, a b-tree, a content addressable memory (CAM), a binary tree, a hash table, and the like. The address mapping table may be referred to interchangeably as a Group Allocation Table (GAT), logical-to-physical address map, or the like.

"Mapping table cache" refers to a data structure configured to associate an LBA and/or an LBA range with a physical block address and/or a physical block address range. In one embodiment, the mapping table cache may store a portion of an address mapping table for faster access to relevant entries of the address mapping table. … more "Mapping table cache" refers to a data structure configured to associate an LBA and/or an LBA range with a physical block address and/or a physical block address range. In one embodiment, the mapping table cache may store a portion of an address mapping table for faster access to relevant entries of the address mapping table.

"Secure communication channel" refers to a set of one or more protocols, software, hardware, and/or firmware components modules or apparatus configured to work together or alone to communicate commands, responses, and/or data between a sending device and a receiving device in a secure manner. In one embodiment, a secure communication channel comprises a way of transferring data that is resistant to overhearing and tampering. ("Secure channel" on Wikipedia. Nov. 2, 2019. Modified. Accessed Nov. 12, 2019.)In certain embodiments, a secure communication channel comprises an out of band channel which is a separate physical or logical communication channel between the sender and the receiver. The out of band channel may comprise a separate physical connection and wire with a different interface or a separate logical channel that uses a shared physical communication bus but the communication bus and protocol are configured such that the sender and receiver can communicate in an authenticate and secure manner. … more "Secure communication channel" refers to a set of one or more protocols, software, hardware, and/or firmware components modules or apparatus configured to work together or alone to communicate commands, responses, and/or data between a sending device and a receiving device in a secure manner. In one embodiment, a secure communication channel comprises a way of transferring data that is resistant to overhearing and tampering. ("Secure channel" on Wikipedia. Nov. 2, 2019. Modified. Accessed Nov. 12, 2019.)In certain embodiments, a secure communication channel comprises an out of band channel which is a separate physical or logical communication channel between the sender and the receiver. The out of band channel may comprise a separate physical connection and wire with a different interface or a separate logical channel that uses a shared physical communication bus but the communication bus and protocol are configured such that the sender and receiver can communicate in an authenticate and secure manner.

"Start event" refers to an event designated to indicate a suitable starting point for a time measurement for the execution of a storage operation. … more "Start event" refers to an event designated to indicate a suitable starting point for a time measurement for the execution of a storage operation.

"Data bus" refers to a communication bus used to exchange one or more of data bits between two electronic circuits, components, chips, die, and/or systems. A data bus may include one or more signal/control lines. A sender, such as a controller, may send data signals over one or more control lines of the data bus in parallel (operating as a parallel bus) or in series (operating as a serial bus). A data bus may include the hardware, control line(s), software, firmware, logic, and/or the communication protocol used to operate the data bus.Examples data buses may include 8-bit buses having 8 control lines, 16-bit buses having 16 control lines, 32-bit buses having 32 control lines, 64-bit buses having 64 control lines, and the like. Control lines may carry exclusively communication data, exclusively address data, exclusively control data, or any combination of these types of data.In one embodiment, a single data bus may be shared by a plurality of components, such as memory die. When multiple chips or memory die share a data bus, that data may be accessed or transferred by a single memory die or by all the memory die in parallel based on signals on a chip enable control line.A data bus may operate, and be configured, according to an industry standard or based on a proprietary protocol and design. Multiple control line of a data bus may be used in parallel and may latch data into latches of a destination component according to a clocking signal, data strobe signal ("DQS"), or clock, such as strobe signal. In certain embodiments, a control bus and a data bus together may form a communication bus between a sender and a receiver. … more "Data bus" refers to a communication bus used to exchange one or more of data bits between two electronic circuits, components, chips, die, and/or systems. A data bus may include one or more signal/control lines. A sender, such as a controller, may send data signals over one or more control lines of the data bus in parallel (operating as a parallel bus) or in series (operating as a serial bus). A data bus may include the hardware, control line(s), software, firmware, logic, and/or the communication protocol used to operate the data bus.Examples data buses may include 8-bit buses having 8 control lines, 16-bit buses having 16 control lines, 32-bit buses having 32 control lines, 64-bit buses having 64 control lines, and the like. Control lines may carry exclusively communication data, exclusively address data, exclusively control data, or any combination of these types of data.In one embodiment, a single data bus may be shared by a plurality of components, such as memory die. When multiple chips or memory die share a data bus, that data may be accessed or transferred by a single memory die or by all the memory die in parallel based on signals on a chip enable control line.A data bus may operate, and be configured, according to an industry standard or based on a proprietary protocol and design. Multiple control line of a data bus may be used in parallel and may latch data into latches of a destination component according to a clocking signal, data strobe signal ("DQS"), or clock, such as strobe signal. In certain embodiments, a control bus and a data bus together may form a communication bus between a sender and a receiver.

"Power down operation" refers to an operation that may include a number of steps or operations that a storage controller, electronic components thereof, or other electronic component takes in preparing have a power supply turned off. … more "Power down operation" refers to an operation that may include a number of steps or operations that a storage controller, electronic components thereof, or other electronic component takes in preparing have a power supply turned off.

"Latency data" refers to data that identifies or may be used to determine a latency for an associated activity, event, or operation, such as a storage operation. … more "Latency data" refers to data that identifies or may be used to determine a latency for an associated activity, event, or operation, such as a storage operation.

"Security module" refers to any hardware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to monitor, manage, maintain, or preserve or protect one or more electronic components from intrusion, malware, viruses, and the like. A security module may also be responsible for other cryptographic features, functions, and digital keys in relation to operations of a system the security module is decided to protect and service. … more "Security module" refers to any hardware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to monitor, manage, maintain, or preserve or protect one or more electronic components from intrusion, malware, viruses, and the like. A security module may also be responsible for other cryptographic features, functions, and digital keys in relation to operations of a system the security module is decided to protect and service.

"Flash logical block address translation operation" refers to an operation that involves the FLASH translation layer. In particular, a flash logical block address translation operation may include an operation to read from, write to, or manage data or metadata relating to operation of a FLASH translation layer. … more "Flash logical block address translation operation" refers to an operation that involves the FLASH translation layer. In particular, a flash logical block address translation operation may include an operation to read from, write to, or manage data or metadata relating to operation of a FLASH translation layer.

"Physical erase block" refers to a smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die). … more "Physical erase block" refers to a smallest storage unit within a given memory die that can be erased at a given time (e.g., due to the wiring of storage cells on the memory die).

"Control bus" refers to a communication bus used to exchange one or more of data, address information, control signals, clock signals, and the like, between two electronic circuits, components, chips, die, and/or systems. A control bus may comprise 1 or more control lines, be configured to operate as a parallel bus or a serial bus, and may include the hardware, control line(s), software, firmware, logic, and/or the communication protocol used to operate the control bus. Typically, a control bus sends control signals to one or more memory die to manage operations on the memory die.In certain embodiments, the control bus sends control signals such as write enable ("WE" or WE#), chip enable ("CE" or "CE#), read enable ("RE" or Re), a clock signal, strobe signal ("DQS"), command latch enable ("CLE"), address latch enable ("ALE"), storage operation commands in the form of operation codes ("OP" codes) and addressing information for a communicated storage operation. In certain embodiments, the control bus may not transfer data relating to a storage operation, such as write data or read data. Instead, write data and read data may be transferred over a data bus. In certain embodiments, a control bus and a data bus together may form a communication bus between a sender and a receiver. … more "Control bus" refers to a communication bus used to exchange one or more of data, address information, control signals, clock signals, and the like, between two electronic circuits, components, chips, die, and/or systems. A control bus may comprise 1 or more control lines, be configured to operate as a parallel bus or a serial bus, and may include the hardware, control line(s), software, firmware, logic, and/or the communication protocol used to operate the control bus. Typically, a control bus sends control signals to one or more memory die to manage operations on the memory die.In certain embodiments, the control bus sends control signals such as write enable ("WE" or WE#), chip enable ("CE" or "CE#), read enable ("RE" or Re), a clock signal, strobe signal ("DQS"), command latch enable ("CLE"), address latch enable ("ALE"), storage operation commands in the form of operation codes ("OP" codes) and addressing information for a communicated storage operation. In certain embodiments, the control bus may not transfer data relating to a storage operation, such as write data or read data. Instead, write data and read data may be transferred over a data bus. In certain embodiments, a control bus and a data bus together may form a communication bus between a sender and a receiver.

"External communication bus" refers to a communication bus that connects or couples to a device or component from a point external to that device or component. … more "External communication bus" refers to a communication bus that connects or couples to a device or component from a point external to that device or component.

"Circuitry" refers to electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes or devices described herein), circuitry forming a memory device (e.g., forms of random-access memory), or circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment). … more "Circuitry" refers to electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes or devices described herein), circuitry forming a memory device (e.g., forms of random-access memory), or circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment).