Dave's PCF WIP: Terms

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candidate read level

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"Candidate read level" refers to a value, setting, configuration, numeric value, offset, or the like for a read level that may provide more accurate sensing of memory cells and/or reading of data from memory cells than a current read level. In certain embodiments, candidate read levels may be predetermined, and may be stored in a repository such as a data structure. In other embodiments, candidate read levels may be predetermined and may be organized into a predefined order which a read scan circuit may be configured to follow in selecting candidate read levels to use in determining a read level to replace a current read level.In still other embodiments, candidate read levels may be calculated based on results of one or more prior sense, and/or read operations (referred to herein as a “scan” or “scans”), that a read scan circuit may perform on a set of storage cells. For example, in one embodiment, the read scan circuit may compare results of a prior scan to results for a current scan using a current candidate read level. If the results with the current candidate read level are more favorable, the read scan circuit may calculate a next candidate read level based on the current candidate read level. If the results with the current candidate read level are less favorable, the read scan circuit may calculate a next candidate read level based on one or more prior scans using candidate read levels. In embodiments that determine which candidate read levels to use with successive iterations, a read scan circuit may apply a positive or negative offset to a current read level to determine a next candidate read level.A candidate read level may comprise one of a plurality of read levels positioned generally between a majority of memory cells of cell threshold voltage distributions for two adjacent memory states. It is desirable that candidate read levels result in optimal performance when reading data from memory cells programmed to one of the two adjacent memory states. In one embodiment, at least one of the candidate read levels will produce an optimal result, result in the fewest number of bit errors when reading from one of the adjacent memory states. Such candidate read levels may be referred to as a target read level. A target read level is a read level that results in a smallest or fewest number of activated memory cells in relation to other candidate read levels that may be iteratively checked. In another embodiment, the target read level is a read level that results in a smallest or fewest number of bit errors or bit error rate or estimated bit error rate from a read set of memory cells in relation to other candidate read levels that may be iteratively checked.