16869424

Paragraph Number

5

This disclosure further relates to an apparatus. This apparatus comprises a three-dimensional memory array of memory cells, a die controller, and a read scan circuit. The die controller is configured to execute storage operations with the memory cells. The read scan circuit iteratively scans a set of memory cells using a first set of candidate read levels until a candidate read level activates the fewest number of memory cells in relation to other candidate read levels within that first set of candidate read levels. The read scan circuit then determines a first read level for a first memory state based on the candidate read level that activates the fewest number of memory cells. The read scan circuit retrieves a correlation between the first memory state and a second memory state. The read scan circuit then determines a second read level for the second memory state using the correlation and sets the first read level and second read level for subsequent read operations.

Added by DJM 12 2021