16869424

Paragraph Number

6

Finally, this disclosure relates to a system comprising a non-volatile memory array and a storage controller. The non-volatile memory array comprises a plurality of memory dies. The storage controller comprises a read/write circuit, a read scan circuit, an error correction code decoder, and a calibration circuit. The read/write circuit writes data to memory cells of the plurality of memory dies. The read scan circuit implements read scan operations for non-volatile memory array storage blocks. These read scan operations test sets candidate read levels based on correlations between two memory cell memory states for each storage block. The error correction code decoder determines an estimated bit error rate for data read during the read scan operation. The calibration circuit calibrates memory cells based on the read levels determined by the read scan circuit.

Added by DJM 12 2021