Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US-8380915-A1	For example, if a user application requests 512 bytes of data, and the solid-state storage media 110 can read 800 bytes of data in a read request at substantially the same speed as 512 bytes of data, in one embodiment, the data set read module 402 may read a data set of 800 bytes for adjusting a read voltage threshold, and provide the requested 512 bytes (a subset of the 800 byte data set) to the user application without affecting the read time of the operation. In one embodiment, the data set read module 402 sets a minimum data set request size and retrieves at least the minimum data set request size amount of data for each read request, even if the read request is for less than the minimum data set request size. The minimum data set request size, in certain embodiments, may be selected to fit within a boundary of one or more ECC chunks, one or more pages, one or more erase blocks, within excess bandwidth of the solid-state storage media 110, or the like. In one embodiment, the minimum data set request size may be selected based on an architecture or geometry of the solid-state storage media 110, the read data pipeline 108, or the like.	195	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, the data set read module 402, when reading a data set of sample data in response to a testing operation, periodically, during monitoring, or the like, may size the sample data set to fit within excess read bandwidth of the solid-state storage media 110. By sizing sample data to fit within excess read bandwidth of the solid-state storage media 110, in one embodiment, reading the sample data may not affect a read bandwidth for servicing read requests to the solid-state storage media 110 or a read throughput of the solid-state storage media 110. In one embodiment, the data set read module 402 may read a data set from the solid-state storage media 110 with a greater amount of data than is requested by a read request to provide a greater sample size of bits for the configuration module 352 to use to determine an adjustment to a read voltage threshold, or the like. A sample size that is greater than an amount of data requested, in certain embodiments, may improve the accuracy of a read voltage threshold adjustment.	194	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The data error may occur due to a shift in a voltage level retained in one or more storage cells of the solid-state storage media 110. This retained voltage level of a storage cell is referred to herein as a read voltage level. The read error module 420, in one embodiment, reads the data set as part of a testing operation. The configuration module 352 may conduct the testing operation in response to the data error, in response to a scheduled maintenance operation, in response to an initial calibration operation, or the like. The data set used by the read error module 420 may come from a client-requested packet, or may be sample data read as part of the testing operation.	193	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the read error module 420 reads the data set in response to a data error identified in the data set. For example, the ECC decoder 322 or another module may determine that a data error has occurred. In one embodiment, the data error is an uncorrectable bit error that the ECC decoder 322 does not have enough information to correct. Specifically, the ECC decoder 322, in one embodiment, is configured to detect and correct up to a certain number of bits (# of Bits in Error-#BER) in error in a data set. When the number of bits in error exceeds the #BER, the ECC decoder 322 may signal an uncorrectable data error, an uncorrectable bit error, or the like.	192	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the monitor module 418 monitors data sets that are read from the solid-state storage media 110 in response to read requests from a computer 112 or other client 114. The monitor module 418 may monitor each data set that is read from the solid-state storage media 110 or may select certain data sets that are read from the solid-state storage media 110, at predefined intervals, in response to a command or directive from a storage client, or the like. By using the monitor module 418 to monitor data sets that are read from the solid-state storage media 110, the configuration module 352 may adjust read voltage thresholds for the solid-state storage media 110 dynamically, preventing uncorrectable data errors from occurring.	191	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In the depicted embodiment, the data set read module 402 includes a monitor module 418 and a read error module 420. The data set read module 402, in one embodiment, may read the data set using the monitor module 418 and/or the read error module 420.	190	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	As described above, a bias is a preference, probability, or tendency of values for bits within a set of bits to exhibit a specific data pattern. In one embodiment, the known bias is a known ratio of binary ones and binary zeroes within a set of bits or groupings of sets of bits. The known ratio, in one embodiment, may be expressed as a proportion or percentage between zero and one, a ratio of zero representing a bias of exclusively one value and a ratio of one representing a bias of exclusively the other value. In one embodiment, the known ratio is greater than zero and less than one, meaning that the known ratio is offset between a ratio of exclusively one binary value and a ratio of exclusively the opposite binary. If the known ratio is greater than zero and less than one, a deviation in the read bias of the data set may occur in either direction from the known ratio and still remain detectable by the configuration module 352.	189	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the data set may be sized relative to a biasing scheme that the bias module 318 employs to bias packets. For example, in one embodiment, the data set may be sized based on the period of a deterministic sequence, such as a pseudorandom binary sequence that the bias module 318 uses to bias packets. The closer the size of the data set is to an integer multiple of the period of the pseudorandom binary sequence, the more likely it is that the bias of the resulting data set will match the known bias. In a further embodiment, the bias module 318 may guarantee that a data set of a predefined size has a bias that does not deviate from the known bias by more than a threshold amount. The threshold amount may range from zero to a given integer value or percentage value.	188	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the storage I/O bus 210 is comprised of one or more independent I/O buses (“IIOBa-m” comprising 210a.a-m, 210n.a-m) wherein the solid-state storage elements within each column share one of the independent I/O buses that accesses each solid-state storage element 216, 218, 220 in parallel so that all banks 214 are accessed simultaneously. For example, one channel of the storage I/O bus 210 may access a first solid-state storage element 216a, 218a, 220a of each bank 214a-n simultaneously. A second channel of the storage I/O bus 210 may access a second solid-state storage element 216b, 218b, 220b of each bank 214a-n simultaneously. Each row of solid-state storage element 216a, 216b, 216m is accessed simultaneously. In one embodiment, where solid-state storage elements 216, 218, 220 are multi-level (physically stacked), all physical levels of the solid-state storage elements 216, 218, 220 are accessed simultaneously. As used herein, “simultaneously” also includes near simultaneous access where devices are accessed at slightly different intervals to avoid switching noise. Simultaneously is used in this context to be distinguished from a sequential or serial access wherein commands and/or data are sent individually one after the other.	60	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Beneficially, sequentially writing packets facilitates a more even use of the solid-state storage media 110 and allows the solid-storage device controller 202 to monitor storage hot spots and level usage of the various logical pages in the solid-state storage media 110. Sequentially writing packets also facilitates a powerful, efficient garbage collection system, which is described in detail below. One of skill in the art will recognize other benefits of sequential storage of data packets.	70	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In a copy operation, the index includes an entry for the original requested data mapped to a number of packets stored in the solid-state storage media 110. When a copy is made, a new copy of the requested data is created and a new entry is created in the index mapping the new copy of the requested data to the original packets. The new copy of the requested data is also written to the solid-state storage media 110 with its location mapped to the new entry in the index. The new copy of the requested data packets may be used to identify the packets within the original requested data that are referenced in case changes have been made in the original requested data that have not been propagated to the copy of the requested data and the index is lost or corrupted.	69	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In a read, modify, write operation, data packets associated with requested data are located and read in a read operation. Data segments of the modified requested data that have been modified are not written to the location from which they are read. Instead, the modified data segments are again converted to data packets and then written sequentially to the next available location in the logical page currently being written. The index entries for the respective data packets are modified to point to the packets that contain the modified data segments. The entry or entries in the index for data packets associated with the same requested data that have not been modified will include pointers to original location of the unmodified data packets. Thus, if the original requested data is maintained, for example to maintain a previous version of the requested data, the original requested data will have pointers in the index to all data packets as originally written. The new requested data will have pointers in the index to some of the original data packets and pointers to the modified data packets in the logical page that is currently being written.	68	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, packets are written sequentially to the solid-state storage media 110. For example, packets are streamed to the storage write buffers of a bank 214a of storage elements 216 and when the buffers are full, the packets are programmed to a designated logical page. Packets then refill the storage write buffers and, when full, the packets are written to the next logical page. The next logical page may be in the same bank 214a or another bank (e.g. 214b). This process continues, logical page after logical page, typically until a logical erase block (“LEB”) is filled. In another embodiment, the streaming may continue across logical erase block boundaries with the process continuing, logical erase block after logical erase block.	67	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	An erase block erase command may be sent out to erase an erase block over the storage I/O bus 210 with a particular erase block address to erase a particular erase block. Typically, an erase block erase command may be sent over the parallel paths of the storage I/O bus 210 to erase a logical erase block, each with a particular erase block address to erase a particular erase block. Simultaneously a particular bank (e.g. Bank 0214a) is selected over the storage control bus 212 to prevent erasure of similarly addressed erase blocks in all of the banks (Banks 1-N 214b-n). Alternatively, no particular bank (e.g. Bank 0214a) is selected over the storage control bus 212 to enable erasure of similarly addressed erase blocks in all of the banks (Banks 1-N 214b-n) simultaneously. Other commands may also be sent to a particular location using a combination of the storage I/O bus 210 and the storage control bus 212. One of skill in the art will recognize other ways to select a particular storage location using the bi-directional storage I/O bus 210 and the storage control bus 212.	66	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Similarly, satisfying a read command on the storage I/O bus 210 requires a simultaneous signal on the storage control bus 212 to select a single bank 214a and the appropriate page within that bank 214a. In one embodiment, a read command reads an entire page, and because there are multiple solid-state storage elements 216a, 216b, 216m in parallel in a bank 214, an entire logical page is read with a read command. However, the read command may be broken into subcommands, as will be explained below with respect to bank interleave. A logical page may also be accessed in a write operation.	65	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Typically, when a packet is written to a particular location within a solid-state storage element 216, 218, 220, wherein the packet is intended to be written to a location within a particular page which is specific to a particular physical erase block of a particular storage element of a particular bank, a physical address is sent on the storage I/O bus 210 and followed by the packet. The physical address contains enough information for the solid-state storage element 216, 218, 220 to direct the packet to the designated location within the page. Since all storage elements in a column of storage elements (e.g. SSS 0.0-SSS N.0216a, 218a, 220a) are accessed simultaneously by the appropriate bus within the storage I/O bus 210a.a, to reach the proper page and to avoid writing the data packet to similarly addressed pages in the column of storage elements (SSS 0.0-SSS N.0216a, 218a, 220a), the bank 214a that includes the solid-state storage element SSS 0.0216a with the correct page where the data packet is to be written is simultaneously selected by the storage control bus 212.	64	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	This group of pages in a bank 214 of solid-state storage elements 216a, 216b, 216m of 80 kB may be called a logical page or virtual page. Similarly, an erase block of each storage element 216a-m of a bank 214a may be grouped to form a logical erase block or a virtual erase block. In one embodiment, an erase block of pages within a solid-state storage element 216, 218, 220 is erased when an erase command is received within a solid-state storage element 216, 218, 220. Whereas the size and number of erase blocks, pages, planes, or other logical and physical divisions within a solid-state storage element 216, 218, 220 are expected to change over time with advancements in technology, it is to be expected that many embodiments consistent with new configurations are possible and are consistent with the general description herein.	63	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, each solid-state storage element 216, 218, 220 is partitioned into erase blocks and each erase block is partitioned into pages. An erase block on a solid-state storage element 216, 218220 may be called a physical erase block or “PEB.” A typical page is 2000 bytes (“2 kB”). In one example, a solid-state storage element (e.g. SSS 0.0) includes two registers and can program two pages so that a two-register solid-state storage element 216, 218, 220 has a capacity of 4 kB. A bank 214 of 20 solid-state storage elements 216a, 216b, 216m would then have an 80 kB capacity of pages accessed with the same address going out the channels of the storage I/O bus 210.	62	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Typically, banks 214a-n are independently selected using the storage control bus 212. In one embodiment, a bank 214 is selected using a chip enable or chip select. Where both chip select and chip enable are available, the storage control bus 212 may select one level of a multi-level solid-state storage element 216, 218, 220. In other embodiments, other commands are used by the storage control bus 212 to individually select one level of a multi-level solid-state storage element 216, 218, 220. Solid-state storage elements 216, 218, 220 may also be selected through a combination of control and of address information transmitted on storage I/O bus 210 and the storage control bus 212.	61	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Solid-State Storage Device Controller	71	Added by DJM 3 2021	3/12/21, 12:00 AM

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