"Bad word line" refers to a word line that is not available for use to read or write data to storages cells, memory cells of the word line. A bad word line may refer to a single physical word line (a physical page) or a plurality of physical word lines (physical page), that together form a logical word line, logical page. Thus, depending on the context bad word line may refer to a bad physical page and/or bad logical page.There are a number of reasons, causes, or circumstances that may result in a word line being marked, tracked, or otherwise identified as a bad word line. For example, a word line may have an electrical short between a structure of the word line and another structure in a non-volatile memory array. In another example, the memory cells of a word line may be worn to the point that the word line can no longer be reliably used to store and read data. Said another way, a bad word line may have too many errors to be useable, or may have been retired from further use, or may have failed. Alternatively, or in addition, memory cells of a word line may have such poor performance that the word line can no longer be used and still need operating performance requirements or expectations.Bad word lines may be designated as such when a non-volatile memory array is manufactured and/or as word lines become bad word lines as the word lines are used. In certain embodiments, … more "Bad word line" refers to a word line that is not available for use to read or write data to storages cells, memory cells of the word line. A bad word line may refer to a single physical word line (a physical page) or a plurality of physical word lines (physical page), that together form a logical word line, logical page. Thus, depending on the context bad word line may refer to a bad physical page and/or bad logical page.There are a number of reasons, causes, or circumstances that may result in a word line being marked, tracked, or otherwise identified as a bad word line. For example, a word line may have an electrical short between a structure of the word line and another structure in a non-volatile memory array. In another example, the memory cells of a word line may be worn to the point that the word line can no longer be reliably used to store and read data. Said another way, a bad word line may have too many errors to be useable, or may have been retired from further use, or may have failed. Alternatively, or in addition, memory cells of a word line may have such poor performance that the word line can no longer be used and still need operating performance requirements or expectations.Bad word lines may be designated as such when a non-volatile memory array is manufactured and/or as word lines become bad word lines as the word lines are used. In certain embodiments,

"Word line" refers to a structure within a memory array comprising a set of memory cells. The memory array is configured such that the operational memory cells of the word line are read or sensed during a read operation. Similarly, the memory array is configured such that the operational memory cells of the word line are read, or sensed, during a read operation. A word line may also be referred to as a physical page or page for short. A physical word line may span a single plane within a memory die. Two or more physical word lines, for example on the same row of a non-volatile memory array may form a logical word line, also referred to as a logical page. … more "Word line" refers to a structure within a memory array comprising a set of memory cells. The memory array is configured such that the operational memory cells of the word line are read or sensed during a read operation. Similarly, the memory array is configured such that the operational memory cells of the word line are read, or sensed, during a read operation. A word line may also be referred to as a physical page or page for short. A physical word line may span a single plane within a memory die. Two or more physical word lines, for example on the same row of a non-volatile memory array may form a logical word line, also referred to as a logical page.

"XOR module" refers to any hardware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to compute, modify, adjust, or calculate XOR parity data. In certain embodiments, the XOR module applies a binary XOR function to two operands and produces a result which is the bitwise XOR of both operands. … more "XOR module" refers to any hardware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to compute, modify, adjust, or calculate XOR parity data. In certain embodiments, the XOR module applies a binary XOR function to two operands and produces a result which is the bitwise XOR of both operands.

"Complete source storage block" refers to a source storage block comprising a data section having exclusively valid data and a valid parity section. A complete source storage block has no invalid data, failed word lines, or bad word lines. … more "Complete source storage block" refers to a source storage block comprising a data section having exclusively valid data and a valid parity section. A complete source storage block has no invalid data, failed word lines, or bad word lines.

"Classifier" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to distinguish fragmented source storage blocks from other storage blocks in a non-volatile memory array. … more "Classifier" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to distinguish fragmented source storage blocks from other storage blocks in a non-volatile memory array.

"Fill data" refers to one or more data blocks that comprise valid data and are used to replace invalid data within a storage block, such as a fragmented source storage block. Relocating fill data may include updating a physical block address associated with the logical block address for the data block that includes the fill data. … more "Fill data" refers to one or more data blocks that comprise valid data and are used to replace invalid data within a storage block, such as a fragmented source storage block. Relocating fill data may include updating a physical block address associated with the logical block address for the data block that includes the fill data.

"Source storage block" refers to a storage block that supplies data blocks for a merging, combining, or folding operation in which data blocks from two or more source storage blocks are combined to write the data blocks in a destination storage block. In one embodiment, the source storage blocks, and destination storage block are configured such that the data block fit within the destination storage block without any remaining data, or data blocks, that exceed the storage capacity of the destination storage block. For example, if the source storage blocks are single level cell (SLC) storage blocks that each hold one bit per memory cell, then the destination storage block is an Multi-level cell (MLC, two bits per memory cell) storage block, a tri-level cell (TLC, three bits per memory cell), a Quad-level cell (QLC, four bits per memory cell), a Penta-level cell (PLC, five bits per memory cell), or the like. … more "Source storage block" refers to a storage block that supplies data blocks for a merging, combining, or folding operation in which data blocks from two or more source storage blocks are combined to write the data blocks in a destination storage block. In one embodiment, the source storage blocks, and destination storage block are configured such that the data block fit within the destination storage block without any remaining data, or data blocks, that exceed the storage capacity of the destination storage block. For example, if the source storage blocks are single level cell (SLC) storage blocks that each hold one bit per memory cell, then the destination storage block is an Multi-level cell (MLC, two bits per memory cell) storage block, a tri-level cell (TLC, three bits per memory cell), a Quad-level cell (QLC, four bits per memory cell), a Penta-level cell (PLC, five bits per memory cell), or the like.

"Whole source storage block" refers to a source storage block formed by combining a fragmented source storage block, fill data, and a valid parity section where the fill data is of a sufficient quantity to replace invalid data within the fragmented source storage block. … more "Whole source storage block" refers to a source storage block formed by combining a fragmented source storage block, fill data, and a valid parity section where the fill data is of a sufficient quantity to replace invalid data within the fragmented source storage block.

"String" refers to a structural sub-dividing of a word line within a non-volatile memory array. In certain embodiments, a word line is divided into four strings. If should be noted that a string is distinct, different from, and not to be confused with a NAND string. A string is associated with a number of logical pages depending on how many bits are stored in each memory cell of the word line. If the word line stores one bit per memory cell, then each string is associated with a single logical page. If the word line stores two bits per memory cell, then each string is associated with two logical pages. If the word line stores three bits per memory cell, then each string is associated with three logical pages. If the word line stores four bits per memory cell, then each string is associated with four logical pages. … more "String" refers to a structural sub-dividing of a word line within a non-volatile memory array. In certain embodiments, a word line is divided into four strings. If should be noted that a string is distinct, different from, and not to be confused with a NAND string. A string is associated with a number of logical pages depending on how many bits are stored in each memory cell of the word line. If the word line stores one bit per memory cell, then each string is associated with a single logical page. If the word line stores two bits per memory cell, then each string is associated with two logical pages. If the word line stores three bits per memory cell, then each string is associated with three logical pages. If the word line stores four bits per memory cell, then each string is associated with four logical pages.

"Buffer memory" refers to an area of a memory media configured to temporarily store a set of data, particularly data being sent to or received from another component or device. In certain aspects, the memory media used for the instruction buffer may be read only memory (ROM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or the like. … more "Buffer memory" refers to an area of a memory media configured to temporarily store a set of data, particularly data being sent to or received from another component or device. In certain aspects, the memory media used for the instruction buffer may be read only memory (ROM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or the like.

"Reverse XOR operation" refers to removing XOR parity data accumulated for data of a particular memory location by performing an additional XOR operation with the accumulated XOR parity data and data in the particular memory location. A reverse XOR operation backs out, reverses, or removes the influence of data used to generate original XOR parity data. … more "Reverse XOR operation" refers to removing XOR parity data accumulated for data of a particular memory location by performing an additional XOR operation with the accumulated XOR parity data and data in the particular memory location. A reverse XOR operation backs out, reverses, or removes the influence of data used to generate original XOR parity data.

"Stager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to convert, manipulate, or configure a fragmented source storage block to form a whole source storage block from at least a portion of the fragmented source storage block. In one embodiment, the stager is configured such that a majority of data of the fragmented source storage block is not differential data and remains on memory die of a non-volatile memory array as part of forming the whole source storage block. … more "Stager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to convert, manipulate, or configure a fragmented source storage block to form a whole source storage block from at least a portion of the fragmented source storage block. In one embodiment, the stager is configured such that a majority of data of the fragmented source storage block is not differential data and remains on memory die of a non-volatile memory array as part of forming the whole source storage block.

"Non-volatile storage media" refers to any hardware, device, component, element, or circuit configured to maintain an alterable physical characteristic (deleted) used to represent a binary value of zero or one after a primary power source is removed. Non-volatile storage media may be used interchangeably herein with the term non-volatile memory media. … more "Non-volatile storage media" refers to any hardware, device, component, element, or circuit configured to maintain an alterable physical characteristic (deleted) used to represent a binary value of zero or one after a primary power source is removed. Non-volatile storage media may be used interchangeably herein with the term non-volatile memory media.

"Read error" refers to an error condition in which when data of a logical page is read the read data includes too many errors to practically use the read result. Typically, in response to a read error remediation operations are initiated to re-create, recovery, or determine appropriate data values for the data of a logical page that experiences the read error. … more "Read error" refers to an error condition in which when data of a logical page is read the read data includes too many errors to practically use the read result. Typically, in response to a read error remediation operations are initiated to re-create, recovery, or determine appropriate data values for the data of a logical page that experiences the read error.

"Consolidation manager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to combine two or more storage blocks into a single destination storage block. … more "Consolidation manager" refers to any hardware, software, firmware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to combine two or more storage blocks into a single destination storage block.

"Programming voltage" refers to a voltage level configured change a characteristic of a memory cell from a first state (often, an erased state) to a second state. A program voltage may also be referred to as a write voltage.In certain embodiments, the memory cells may comprise transistors and the programming voltage is a voltage level at, or above which, a threshold voltage for the memory cell changes to a new level. … more "Programming voltage" refers to a voltage level configured change a characteristic of a memory cell from a first state (often, an erased state) to a second state. A program voltage may also be referred to as a write voltage.In certain embodiments, the memory cells may comprise transistors and the programming voltage is a voltage level at, or above which, a threshold voltage for the memory cell changes to a new level.

"Junction leakage current" refers to an amount of current measured in Amperes for a variety of electronic components, switches, control lines, paths and the like in an electronic circuit path between one or more word lines in a non-volatile memory array and a leakage detection circuit. … more "Junction leakage current" refers to an amount of current measured in Amperes for a variety of electronic components, switches, control lines, paths and the like in an electronic circuit path between one or more word lines in a non-volatile memory array and a leakage detection circuit.

"Least significant bit" or “LSB” refers to the bit position in a binary integer giving the units value, that is, determining whether the number is even or odd. The LSB is sometimes referred to as the low-order bit or right-most bit, due to the convention in positional notation of writing less significant digits further to the right. It is analogous to the least significant digit of a decimal integer, which is the digit in the ones (right-most) position. (See “Bit numbering”, Wikipedia, Jan. 29, 2019; Accessed May 7, 2020.) … more "Least significant bit" or “LSB” refers to the bit position in a binary integer giving the units value, that is, determining whether the number is even or odd. The LSB is sometimes referred to as the low-order bit or right-most bit, due to the convention in positional notation of writing less significant digits further to the right. It is analogous to the least significant digit of a decimal integer, which is the digit in the ones (right-most) position. (See “Bit numbering”, Wikipedia, Jan. 29, 2019; Accessed May 7, 2020.)

"Variable current source" refers to a circuit, sub-circuit, circuitry, electronic component, hardware, software, firmware, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to serve as a current source for current at a predetermined and adjustable magnitude. … more "Variable current source" refers to a circuit, sub-circuit, circuitry, electronic component, hardware, software, firmware, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to serve as a current source for current at a predetermined and adjustable magnitude.

"Even leakage code" refers to a leakage code configured to reference a level of leakage current from evenly numbered word lines in a non-volatile memory array (either within a single plane or across multiple planes of a memory die). … more "Even leakage code" refers to a leakage code configured to reference a level of leakage current from evenly numbered word lines in a non-volatile memory array (either within a single plane or across multiple planes of a memory die).