Paragraph 56
Paragraph 56
Matter Number
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Paragraph Number
56
Application Number
13189402
Reference Case 1
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Reference Case 2
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Created
3/12/21, 12:00 AM
Modified
3/12/21, 12:00 AM
Id
2,629
Content
In one embodiment, solid-state storage elements that share a common storage I/O bus 210a (e.g. 216b, 218b, 220b) are packaged together. In one embodiment, a solid-state storage element 216, 218, 220 may have one or more dies per chip with one or more chips stacked vertically and each die may be accessed independently. In another embodiment, a solid-state storage element (e.g. SSS 0.0216a) may have one or more virtual dies per die and one or more dies per chip and one or more chips stacked vertically and each virtual die may be accessed independently. In another embodiment, a solid-state storage element SSS 0.0216a may have one or more virtual dies per die and one or more dies per chip with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.
Notes
Added by DJM 3 2021