Paragraph 37
Paragraph 37
Application
Dedicated termination dies for memory systems
Matter Number
FSP1845
Paragraph Number
37
Application Number
16/146,238
Reference Case 1
FSP1845
Reference Case 2
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Created
12/22/21, 12:00 AM
Modified
12/22/21, 12:00 AM
Id
6,550
Content
FIG. 1A is a block diagram illustrating a memory system 100, such as a non-volatile memory system. The memory system 100 may include a controller 102 and memory that may be made up of a plurality of memory dies 104. As used herein, the term memory die refers to the set of memory cells (including non-volatile memory cells), and associated circuitry for managing the physical operation of those memory cells, that are formed on a single semiconductor substrate. In addition, the term die, in general, may refer to circuitry or circuit components on a single semiconductor substrate, but may or may not include memory cells to store data. The controller 102 may interface with a host system and transmit command sequences for read, program, and erase operations to the non-volatile memory dies 104. Herein, the controller 102 is referred to as a controller die 102 to identify or highlight that the circuitry of the controller 102 is configured or located on a die separate from the plurality of memory dies 104. The controller die 102 and each of the memory dies 104 may be configured or function as transceiver circuits, in that they each can transmit and receive signals. As described in further detail below, the controller die 102 and the plurality of memory dies 104 are configured to communicate with each other over a plurality of transmission lines.
Notes
Added by DJM 12 2021