Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	US-20150012794-A1	The non-volatile memory media 122 may comprise one or more non-volatile memory elements 123, which may include, but are not limited to: chips, packages, planes, die, and the like. A non-volatile memory media controller 126 may be configured to manage storage operations on the non-volatile memory media 122, and may comprise one or more processors, programmable processors (e.g., field-programmable gate arrays), or the like. In some embodiments, the non-volatile memory media controller 126 is configured to store data on (and read data from) the non-volatile memory media 122 in the contextual, log format described above, and to transfer data to/from the non-volatile memory device 120, and so on.	64	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The storage management layer 130 may be configured to provide storage services to one or more storage clients 116. The storage clients 116 may include local storage clients 116 operating on the computing device 110 and/or remote, storage clients 116 accessible via the network (and network interface 113). The storage clients 116 may include, but are not limited to: operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.	52	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The computing device 110 may further comprise a non-transitory, computer readable storage media 114. The computer readable storage media 114 may comprise executable instructions configured to cause the computing device 110 (e.g., processor 111) to perform steps of one or more of the methods disclosed herein. Alternatively, or in addition, the storage management layer 130 and/or one or more modules thereof may be embodied as one or more computer readable instructions stored on the non-transitory storage media 114.	51	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	FIG. 1A is a block diagram of one embodiment of a system 100 comprising a configuration module 150. The configuration module 150 may be part of and/or in communication with a storage management layer (SML) 130. The SML 130 may operate on a non-volatile memory system 102 of a computing device 110, which may comprise a processor 111, volatile memory 112, and a communication interface 113. The processor 111 may comprise one or more central processing units, one or more general-purpose processors, one or more application-specific processors, one or more virtual processors (e.g., the computing device 110 may be a virtual machine operating within a host), one or more processor cores, or the like. The communication interface 113 may comprise one or more network interfaces configured to communicatively couple the computing device 110 (and/or non-volatile memory controller 124) to a communication network, such as a Internet Protocol network, a Storage Area Network, or the like.	50	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The log format described herein may allow valid data to be distinguished from invalid data based upon the contents of the non-volatile memory media, and independently of other metadata. As discussed above, invalid data may not be removed from the non-volatile memory media until the memory division comprising the data is reclaimed. Therefore, multiple “versions” of data having the same context may exist on the non-volatile memory media (e.g., multiple versions of data having the same logical addresses). The sequence indicators associated with the data may be used to distinguish invalid versions of data from the current, up-to-date version of the data; the data that is the most recent in the log is the current version, and previous versions may be identified as invalid.	49	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In some embodiments the log format may comprise storing data in an “append only” paradigm. The non-volatile memory controller may maintain a current append point at a media address of the non-volatile memory device. The append point may be a current memory division and/or offset within a memory division. Data may then be sequentially appended from the append point. The sequential ordering of the data, therefore, may be determined based upon the sequence indicator of the memory division of the data in combination with the sequence of the data within the memory division. Upon reaching the end of a memory division, the non-volatile memory controller may identify the “next” available memory division (the next memory division that is initialized and ready to store data). The groomer may reclaim memory divisions comprising invalid, stale, and/or deleted data, to ensure that data may continue to be appended to the media log.	48	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The non-volatile memory controller may be further configured to store data in a log format. As described above, a log format refers to a data format that defines an ordered sequence of storage operations performed on a non-volatile memory media. In some embodiments, the log format comprises storing data in a pre-determined sequence of media addresses of the non-volatile memory media (e.g., within sequential pages and/or erase blocks of the media). The log format may further comprise associating data (e.g., each packet or data segment) with respective sequence indicators. The sequence indicators may be applied to data individually (e.g., applied to each data packet) and/or to data groupings (e.g., packets stored sequentially on a memory division, such as an erase block). In some embodiments, sequence indicators may be applied to memory divisions when the memory divisions are reclaimed (e.g., erased), as described above, and/or when the memory divisions are first used to store data.	47	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In some embodiments, the non-volatile memory controller comprises a groomer, which is configured to reclaim memory divisions (e.g., erase blocks) for reuse. The write out-of-place paradigm implemented by the non-volatile memory controller may result in obsolete or invalid data remaining on the non-volatile memory media. For example, overwriting data X with data Y may result in storing Y on a new memory division (rather than overwriting X in place), and updating the any-to-any mappings of the metadata to identify Y as the valid, up-to-date version of the data. The obsolete version of the data X may be marked as invalid, but may not be immediately removed (e.g., erased), since, as discussed above, erasing X may involve erasing an entire memory division, which is a time-consuming operation and may result in write amplification. Similarly, data that is no longer is use (e.g., deleted or trimmed data) may not be immediately removed. The non-volatile memory media may accumulate a significant amount of invalid data. A groomer process may operate outside of the critical path for servicing storage operations. The groomer process may reclaim memory divisions so that they can be reused for other storage operations. As used herein, reclaiming a memory division refers to erasing the memory division so that new data may be stored/programmed thereon. Reclaiming a memory division may comprise relocating valid data on the memory division to a new location. The groomer may identify memory divisions for reclamation based upon one or more factors, which may include, but are not limited to: the amount of invalid data in the memory division, the amount of valid data in the memory division, wear on the memory division (e.g., number of erase cycles), time since the memory division was programmed or refreshed, and so on.	46	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The non-volatile memory controller may comprise one or more processes that operate outside of the regular path for servicing of storage operations (the “path” for performing a storage operation and/or servicing a storage request). As used herein, the “path for servicing a storage request” or “path for servicing a storage operation” (also referred to as the “critical path”) refers to a series of processing operations needed to service the storage operation or request, such as a read, write, modify, or the like. The path for servicing a storage request may comprise receiving the request from a storage client, identifying the logical addresses of the request, performing one or more storage operations on non-volatile memory media, and returning a result, such as acknowledgement or data. Processes that occur outside of the path for servicing storage requests may include, but are not limited to: a groomer, de-duplication, and so on. These processes may be implemented autonomously and in the background, so that they do not interfere with or impact the performance of other storage operations and/or requests. Accordingly, these processes may operate independent of servicing storage requests.	45	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In some embodiments, the non-volatile memory controller may be configured to store data on one or more asymmetric, write-once media, such as solid-state storage media. As used herein, a “write once” storage medium refers to a storage medium that is reinitialized (e.g., erased) each time new data is written or programmed thereon. As used herein, an “asymmetric” storage medium refers to a storage medium having different latencies for different storage operations. Many types of solid-state storage media are asymmetric; for example, a read operation may be much faster than a write/program operation, and a write/program operation may be much faster than an erase operation (e.g., reading the media may be hundreds of times faster than erasing, and tens of times faster than programming the media). The memory media may be partitioned into memory divisions that can be erased as a group (e.g., erase blocks) in order to, inter alia, account for the asymmetric properties of the media. As such, modifying a single data segment in-place may require erasing the entire erase block comprising the data, and rewriting the modified data to the erase block, along with the original, unchanged data. This may result in inefficient “write amplification,” which may excessively wear the media. Therefore, in some embodiments, the non-volatile memory controller may be configured to write data out-of-place. As used herein, writing data “out-of-place” refers to writing data to different media storage location(s) rather than overwriting the data “in-place” (e.g., overwriting the original physical location of the data). Modifying data out-of-place may avoid write amplification, since existing, valid data on the erase block with the data to be modified need not be erased and recopied. Moreover, writing data out-of-place may remove erasure from the latency path of many storage operations (the erasure latency is no longer part of the critical path of a write operation).	44	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The non-volatile memory media controller 126 may further comprise a multiplexer 249 that is configured to selectively route data and/or commands to/from the write pipeline 240 and the read pipeline 241. In some embodiments, non-volatile memory media controller 126 may be configured to read data while filling a buffer of the write pipeline 240 and/or may interleave one or more storage operations on one or more banks of non-volatile memory elements 123 (not shown).	74	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	Access data, as used herein, comprises metadata, settings, and/or thresholds which the non-volatile memory controller 124, the non-volatile memory media controller 126, a device driver such as the SML 130, or the like may use to access (e.g., read, write, program, and/or erase) a region of the non-volatile memory media 122. Access data may include one or more media parameters or storage thresholds as described below (e.g., read voltage thresholds, a bias for multiple read voltage thresholds, a resistivity threshold, a programming threshold, an erase threshold, a hardware driver level threshold, a storage controller level threshold, or the like), a program/erase cycle count for the region of non-volatile memory media 122, an age of the non-volatile memory media 122 (e.g., time since first powered on, amount of time powered on, or the like), a table with multiple media parameters or storage thresholds, a logical-to-physical mapping for data of a region of non-volatile memory media 122, validity metadata or a validity bitmap for data of a region of non-volatile memory media 122, or other information associated with accessing data of a region of non-volatile memory media 122.	84	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In some embodiments, the non-volatile memory device 120 may be in communication with a host device, such as a computing device 110, over a communications bus, such as the bus 125. In one embodiment, a region of the non-volatile memory media 122 such as a physical or logical page, physical or logical erase block, chip, die, die planes, plurality of chips or dies, or the like, may include multiple ECC chunks. In a further embodiment, each ECC chunk may include or encode data from a user, metadata, a predetermined pattern, or the like. In some embodiments, one or more ECC chunks for a region may encode access data facilitating access to the region, while other ECC chunks may encode other data, such as user data (e.g., workload data stored for a client 116) or the like.	83	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In one embodiment, the primary ECC module 302 may be configured to determine error information using the primary error correcting code to attempt to decode at least one ECC chunk. As used herein, error information comprises data associated with one or more errors or potential errors for one or more ECC chunks. The primary ECC module 302 may determine error information for an ECC chunk by processing the ECC chunk using an ECC decoder or the like. In attempting to decode at least one ECC chunk, the primary ECC module 302 may determine error information either from successfully decoding the at least one ECC chunk, or may determine error information from an unsuccessful attempt to decode the ECC chunk. In various embodiments, error information may include whether or not an ECC chunk is correctable, a number and/or location of bits in error, a raw bit error rate (RBER), an uncorrectable bit error rate (UBER), a ratio of bits which store a binary zero to bits which store a binary one in the decoded data (e.g., a DC balance as described below), or other information related to decoding (or attempting to decode) the at least one ECC chunk using one or more levels of error correcting codes.	82	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In some embodiments, in order to nest multiple layers of error correction, the input data bits for an ECC chunk of the primary ECC module 302 may comprise a secondary ECC chunk generated by the secondary ECC module 304. In this manner, for a systematic ECC code word provided by the primary ECC module 302, the message or input data (e.g., the data other than the check bits for the error correcting code) may comprise one or more secondary or inner ECC code words from the secondary ECC module 304. Thus, in certain embodiments, a configuration module 150 using a systematic code as a primary, outer error correcting code may decode an ECC chunk using a secondary, inner error correcting code even if the primary ECC module 302 determines that the ECC chunk is uncorrectable using the primary, outer error correcting code. In this manner, in one embodiment, the secondary ECC module 304 may provide stronger, higher overhead error protection for at least a subset of ECC chunks of the non-volatile memory device 120, such as the access data described below, enabling the primary ECC module 304 to provide less strong, lower overhead error protection for the rest of the ECC chunks without the added overhead of the stronger protection.	81	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The primary ECC module 302 and the secondary ECC module 304, in a further embodiment, may encode, decode, or otherwise provide error correction and/or detection on at least a portion of the same data, for one or more ECC chunks or the like. For example, the primary ECC module 302 may provide a standard, uniform, or other predetermined level of error correction to all or substantially all data of the non-volatile memory device 120, including one or more segments or portions of data for which the secondary ECC module 304 has already provided error correction. In such embodiments, the primary ECC module 302 may provide a primary, outer layer of error correction around a secondary, inner layer of error correction provided by the secondary ECC module 304 and nested within an ECC chunk of the primary ECC module 302 as described below. As used herein, an inner error correcting code comprises an error correcting code for an ECC chunk embedded or nested within another ECC chunk generated by another, outer error correcting code.	80	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The primary ECC module 302 and the secondary ECC module 304, in certain embodiments, may encode, decode, or otherwise provide error correction and/or detection to different data, different ECC chunks, or the like, so that the different data has different levels or strengths of error protection. For example, the secondary ECC module 304 may provide a stronger error correcting code for one or more ECC chunks than an error correcting code provided by the primary ECC module 302 for the rest of the ECC chunks, as described below. As used herein, one error correcting code is stronger than another error correcting code if the error correcting code is capable of detecting and/or correcting more bit errors per unit of data, detecting and/or correcting data with a higher error rate, or the like. The primary ECC module 302 may provide a lower level of error correction than the secondary ECC module 304 for a majority of data of the non-volatile memory device 120 and the secondary ECC module 304 may provide a higher or stronger level of error correction for a minority of data of the non-volatile memory device 120, such as a predefined type or class of data (e.g., priority data, access data, or the like), as described below.	79	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In one embodiment, an ECC chunk may refer to a code word for the primary error correcting code. In various embodiments, the primary error correcting code may be one of various types of error correcting code, such as a block code, a convolutional code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a low-density parity check (LDPC) code, a Hamming code, a Reed-Solomon code, a turbo code, or the like. In a certain embodiment, the primary error correcting code may be a systematic error correcting code, so that each ECC chunk, or code word, may store data received by an encoder for the primary error correcting code, as well as parity bits, or check bits. A systematic error correcting code, as used herein, may comprise an error correcting code that includes or combines the input data in the output ECC code word or chunk, so that the ECC code word or chunk includes the input data directly. This means that the input data (e.g. the message) is readily identifiable in the ECC code word. In other words, the input data (e.g. the message) is either not transformed/encoded or is encoded/transformed with a unity encoding. A non-systematic code, as used herein, may comprise an error correcting code that encodes or transforms the input data so that the encoded output includes the input data encoded together with other ECC check bits (aka parity bits). This means that the input data (e.g. the message) is not readily identifiable in the ECC code word. An ECC chunk generated by a systematic error correcting code may store ECC check bits or parity bits before the non-encoded input data, after the non-encoded input data, or at one or more other locations within the non-encoded input data. An ECC chunk generated by a non-systematic error correcting code may provide error detection and/or correction using the data encoding itself, with or without separate ECC check bits. In a non-systematic error correcting code, the output may comprise a code word which itself may be considered the ECC check bits.	78	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	The primary ECC module 302, in one embodiment, is configured to determine whether at least one ECC chunk of a non-volatile memory device 120 is correctable using an error correcting code (e.g., a primary error correcting code, an outer error correcting code, or the like). In some embodiments, the error correcting code for the primary ECC module 302 may be referred to as a “primary,” “first,” or “outer” error correcting code, to distinguish it from other error correcting codes that may be used by other modules, such as the secondary ECC module 304. In various embodiments, a means for determining whether at least one ECC chunk of a non-volatile memory device 120 is correctable using a primary or first error correcting code may include a primary ECC module 302, a configuration module 150, a non-volatile memory controller 124, a non-volatile memory media controller 126, a device driver such as an SML 130, a processor 111, a read pipeline 241, other logic hardware and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for determining if the ECC chunk is correctable using a primary or first error correcting code. In a further embodiment, the primary ECC module 302 may be configured to determine primary or first error information using a primary error correcting code to attempt to decode the at least one ECC chunk.	77	Added by DJM 2 2021	2/22/21, 12:00 AM
View Edit Delete	US-20150012794-A1	In the depicted embodiment, the configuration module 150 includes a primary ECC module 302, a secondary ECC module 304, and an adjustment module 306. The primary ECC module 302 and the secondary ECC module 304 may provide different levels of error protection and/or detection and may determine error information for data using one or more of the different levels of error protection. The adjustment module 306 may adjust one or more media parameters for the non-volatile memory media 122, or the like, based at least in part upon error information determined by the primary ECC module 302 and/or the secondary ECC module 304, as described in greater detail below. A level or strength of an error correcting code, as used herein, may comprise a number of bit errors that the error correcting code is capable of detecting and/or correcting, an error rate which the error correcting code is capable of correcting, or the like. A level or strength of an error correcting code may be relative to a number of bits, an overhead or code rate (e.g., a proportion of user data to total data including ECC check bits) for the error correcting code, or the like.	76	Added by DJM 2 2021	2/22/21, 12:00 AM

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