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Access data may be stored in one or more predefined locations in a storage region of the non-volatile memory device 120. For example, the first ECC chunk, the first two ECC chunks, the first N ECC chunks, the Nth one or more ECC chunks, or the like. In certain embodiments, each storage region may comprise access data. In certain embodiments, the access data for a storage region may comprise a media access control (MAC) header or erase block opener for a storage region. In one embodiment, an ECC chunk encoding access data may be protected by a stronger error correcting code than user data or workload data, multiple levels or layers of error correcting codes, or the like to ensure that the access data may be decoded and errors corrected. The adjustment module 306 may use access data for a region, decoded by the primary ECC module 302 and/or the secondary ECC module 304, to read from, write/program, and/or otherwise access other data of the region (e.g., user data, workload data, client data), as described below). |
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In one embodiment, the repetition error correcting code may be the secondary/inner error correcting code, and the secondary ECC module 304 may use the repetition code module 406 to decode the repeated messages. For example, in a certain embodiment, each bit of the access data may be repeated as a message for the repetition error correcting code. In another embodiment, the access data as a whole may be repeated as a message for the repetition error correcting code. |
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The at least one ECC chunk, in one embodiment, may include or encode access data using the repetition error correcting code and/or the secondary/inner error correcting code with the primary/outer error correcting code to provide multiple levels of error correction for the access data. In a further embodiment, additional ECC chunks may include or encode additional data using one level of error correcting code (e.g., the primary/outer error correcting code). ECC chunks encoding data and access data are described in further detail below with regard to FIG. 5A, FIG. 5B, and FIG. 5C. |
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In one embodiment, the repetition code module 406 may include, control, or otherwise cooperate with a decoder for the repetition error correcting code. In a further embodiment, the repetition code module 406 may include, control, or otherwise cooperate with an encoder for the repetition error correcting code. |
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In one embodiment, the repetition code module 406 may determine whether the ECC chunk is correctable using the repetition error correcting code based on the number of identical instances of the repeated message. In another embodiment, the repeated message may be a code word for the secondary/inner error correcting code, and the repetition code module 406 may determine whether the ECC chunk is correctable using the repetition error correcting code based on how many repeated messages are correctable using the secondary/inner error correcting code. In various embodiments, the repetition code module 406 may determine that the ECC chunk is correctable using the repetition error correcting code based on a number of repeated messages satisfying a threshold number for messages having a certain property such as being identical, being decodable with a secondary/inner error correcting code, or the like. |
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A replication or repetition error correcting code, as used herein, may repeat a message (e.g., the input or payload data for an ECC chunk) multiple times to increase the probability that a majority of the repeated messages will be correct. An ECC chunk, which may include a code word for the primary/outer error correcting code or the like, may encode multiple repeated messages (e.g., the input or payload data for the ECC chunk) for the repetition error correcting code. In a further embodiment, the repetition code module 406 may repeat an entire ECC chunk, including a message and ECC check bits for the message, an encoded message, or the like, multiple times. The repetition code module 406, in certain embodiments, may store different copies of a message, an ECC code word, or the like in different storage regions, different sub-regions, different memory elements, or the like, to decrease a probability that different copies will be effected by the same errors. For example, the repetition code module 406 may repeat a message, an ECC code word, or the like on each of a plurality of memory elements of the non-volatile memory media 122, across an array of memory elements or the like, with each memory element storing one copy of the repeated message or ECC code word. As described above, a memory element may comprise a chip, a package, a die plane, a die, a logical or physical erase block, a logical or physical page, or the like. |
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The at least one ECC chunk may include or encode access data encoded with the primary/outer, secondary/inner, and/or repetition error codes, so that error information used by the adjustment module 306 may be based on any of the multiple layers of error correcting codes. In one embodiment, the primary ECC module 302 may be configured to determine primary, or outer error information for the at least one ECC chunk, and the secondary ECC module 304 may be configured to determine secondary, or inner error information for the at least one ECC chunk. Similarly, in a further embodiment, the repetition code module 406 may be configured to determine third, or “repetition” error information by using the repetition error correcting code to attempt to decode the at least one ECC chunk. Then, the error information used by the adjustment module 306 may include the first/primary, second/secondary, and/or third/repetition error information. |
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The repetition code module 406, in one embodiment, is configured to determine whether the at least one ECC chunk encoded with multiple error correcting codes is correctable using a repetition error correcting code. In various embodiments, a means for determining whether the at least one ECC chunk is correctable using a repetition error correcting code may include a repetition code module 406, a configuration module 150, a non-volatile memory controller 124, a non-volatile memory media controller 126, a device driver such as an SML 130, a processor 111, a read pipeline 241, other logic hardware and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for determining if the ECC chunk is correctable using a repetition error correcting code. |
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FIG. 4 depicts another embodiment of a configuration module 150. The configuration module 150, in certain embodiments, may be substantially similar to the configuration module 150 described above with regard to FIG. 1A, FIG. 1B, FIG. 2, and/or FIG. 3. In the depicted embodiment, the configuration module 150 includes a first ECC module 302, a secondary ECC module 304, and an adjustment module 306, which may be configured substantially as described above with regard to FIG. 3. The configuration module 150, in the depicted embodiment, includes a repetition code module 406, an analog information module 408, a control loop module 410, and a header module 412. The secondary ECC module 304, in the depicted embodiment, includes a soft decision module 402 and a DC balance module 404. |
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The storage management layer 130 comprises and/or is communicatively coupled to one or more non-volatile memory devices 120A-N. The non-volatile memory devices 120A-N may include different types of non-volatile memory devices including, but not limited to: solid-state storage devices, hard drives, SAN storage resources, or the like. The non-volatile memory devices 120A-N may comprise respective non-volatile memory media controllers 126A-N and non-volatile memory media 122A-N. As illustrated in FIG. 1B, The SML 130 may provide access to the non-volatile memory devices 120A-N via a traditional block I/O interface 131. Additionally, the SML 130 may provide access to enhanced functionality (large, virtual address space) through the SML interface 132. The metadata 135 may be used to manage and/or track storage operations performed through any of the Block I/O interface 131, SML interface 132, cache interface 133, or other, related interfaces. |
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The non-volatile memory device 120 may comprise non-volatile memory media 122, which may include but is not limited to: NAND flash memory, NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), resistive RAM (RRAM), programmable metallization cell (PMC), conductive-bridging RAM (CBRAM), magneto-resistive RAM (MRAM), dynamic RAM (DRAM), phase change RAM (PRAM or PCM), magnetic storage media (e.g., hard disk, tape), optical storage media, or the like. While the non-volatile memory media 122 is referred to herein as “memory media,” in various embodiments, the non-volatile memory media 122 may more generally comprise a non-volatile recording media capable of recording data, which may be referred to as a non-volatile memory media, a non-volatile storage media, or the like. Further, the non-volatile memory device 120, in various embodiments, may comprise a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like. |
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The computing device 110 may comprise a non-volatile memory controller 124 that is configured to provide storage services to the storage clients 116. The storage clients 116 may include local storage clients 116 operating on the computing device 110 and/or remote, storage clients 116 accessible via the network 115 (and network interface 113). The non-volatile memory controller 124 comprises one or more non-volatile memory devices 120. Although FIG. 1B depicts a single non-volatile memory device 120, the disclosure is not limited in this regard and could be adapted to incorporate any number of non-volatile memory devices 120. |
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FIG. 1B is a block diagram of another embodiment of a system 101 comprising a configuration module 150. As described above, the configuration module 150 may be part of and/or in communication with a storage management layer 130. The SML 130 may operate on a non-volatile memory system 102 of a computing device 110, which, as discussed above, may comprise a processor 111, volatile memory 112, communication interface 113, and non-transitory, computer readable storage media 114. The communication interface 113 may comprise one or more network interfaces configured to communicatively couple the computing device 110 (and/or non-volatile memory controller 124) to a network 115 and/or to one or more remote, network-accessible storage clients 116. |
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In one embodiment, the configuration module 150 is configured to adjust media parameters for the non-volatile memory media 122 in response to receiving a storage request from the SML 130 via a bus 125 or the like. The configuration module 150 may be further configured to transfer data to/from the SML 130 and/or storage clients 116 via the bus 125. Accordingly, the configuration module 150, in some embodiments, may comprise and/or be in communication with one or more direct memory access (DMA) modules, remote DMA modules, bus controllers, bridges, buffers, and so on to facilitate the transfer of storage requests and associated data. In another embodiment, the configuration module 150 may receive storage requests as an API call from a storage client 116, as an IO-CTL command, or the like. The configuration module 150 is described in greater detail below with regard to FIGS. 3 and 4. |
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In one embodiment, the configuration module 150 may comprise executable software code, such as a device driver, SML 130, or the like, stored on the computer readable storage media 114 for execution on the processor 111. In another embodiment the configuration module 150 may comprise logic hardware of one or more of the non-volatile memory devices 120A-N, such as a non-volatile memory media controller 126A-N, a non-volatile memory controller 124, a device controller, a field-programmable gate array (FPGA) or other programmable logic, firmware for an FPGA or other programmable logic, microcode for execution on a microcontroller, an application-specific integrated circuit (ASIC), or the like. In a further embodiment, the configuration module 150 may include a combination of both executable software code and logic hardware. |
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The non-volatile memory system 102, in the depicted embodiment, includes a configuration module 150. The configuration module 150, in one embodiment, is configured to determine whether an error correcting code (ECC) chunk or ECC block for the non-volatile memory device 120 is correctable using a primary or first error correcting code. If the ECC chunk or block is not correctable using the primary error correcting code, the configuration module 150 determines whether the ECC chunk or block is correctable using a secondary or second error correcting code different from the primary error correcting code. If the ECC chunk or block is correctable using the secondary error code, the configuration module 150 uses error information from a decoder for the secondary error correcting code to adjust media parameters for accessing the non-volatile memory media 122. Adjusting media parameters based on multiple levels of error correcting codes for at least one ECC chunk or block allows the non-volatile memory device 120 to store and/or retrieve additional ECC chunks or blocks using a weaker error correcting code (e.g., a code that uses less computational or storage overhead than would otherwise be used, to provide sufficient levels of correctability for the additional ECC chunks or blocks). |
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The SML 130 may further comprise a non-volatile memory device interface 139 configured to transfer data, commands, and/or queries to the non-volatile memory devices 120A-N over a bus 125, which may include, but is not limited to: a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a small computer system interface (SCSI), FireWire, Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network, Infiniband, SCSI RDMA, or the like. The non-volatile memory device interface 139 may communicate with the non-volatile memory devices 120A-N using input-output control (IO-CTL) command(s), IO-CTL command extension(s), remote direct memory access, or the like. |
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The SML 130 may further comprise a log storage module 137 that is configured to store data in a contextual, log format. The contextual, log data format may comprise associating data with persistent contextual metadata, such as the logical address of the data, or the like. The contextual, log format may further comprise associating data with respective sequence identifiers on the non-volatile memory media 122A-N, which define an ordered sequence of storage operations performed on the non-volatile memory devices 120A-N, as described above. |
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The SML 130 may provide storage services through one or more interfaces, which may include, but are not limited to: a block I/O interface, an extended storage management layer interface, a cache interface, and the like. The SML 130 may present a logical address space 134 to the storage clients 116 through one or more interfaces. As discussed above, the logical address space 134 may comprise a plurality of logical addresses, each corresponding to respective media locations on one or more of the non-volatile memory devices 120A-N. The SML 130 may maintain metadata 135 comprising any-to-any mappings between logical addresses and media locations, as described above. |
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The cache interface 133 may expose cache-specific features accessible via the storage management layer 130. Also, in some embodiments, the SML interface 132 presented to the storage clients 116 provides access to data transformations implemented by the non-volatile memory devices 120A-N and/or the non-volatile memory media controllers 126A-N. |
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