Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	2380.2.01	In one embodiment, solid-state storage elements for multiple banks that share a common storage I/O bus 210a row (e.g. 216b, 218b, 220b) are packaged together. In one embodiment, a solid-state storage element 216, 218, 220 may have one or more dies per chip with one or more chips stacked vertically and each die may be accessed independently. In another embodiment, a solid-state storage element (e.g. SSS 0.0216a) may have one or more virtual dies per die and one or more dies per chip and one or more chips stacked vertically and each virtual die may be accessed independently. In another embodiment, a solid-state storage element SSS 0.0216a may have one or more virtual dies per die and one or more dies per chip with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.	95	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The storage controller 152 is substantially similar to the storage controller 152 described in relation to the system 101 of FIG. 1B and may be a solid-state storage device controller 202 described in relation to FIG. 2. The apparatus 200 includes an object request receiver module 260 that receives an object request from one or more requesting devices 155. For example, for a store object data request, the storage controller 152 stores the data segment as a data packet in a data storage device 154 coupled to the storage controller 152. The object request is typically directed at a data segment stored or to be stored in one or more object data packets for an object managed by the storage controller 152. The object request may request that the storage controller 152 create an object to be later filled with data through later object request which may utilize a local or remote direct memory access (“DMA,” “RDMA”) transfer.	66	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The solid state storage 110 is an array of non-volatile solid-state storage elements 216, 218, 220, arranged in banks 214, and accessed in parallel through a bi-directional storage input/output (“I/O”) bus 210. The storage I/O bus 210, in one embodiment, is capable of unidirectional communication at any one time. For example, when data is being written to the solid-state storage 110, data cannot be read from the solid-state storage 110. In another embodiment, data can flow both directions simultaneously. However bi-directional, as used herein with respect to a data bus, refers to a data pathway that can have data flowing in only one direction at a time, but when data flowing one direction on the bi-directional data bus is stopped, data can flow in the opposite direction on the bi-directional data bus.	93	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, at least one solid-state controller 104 is field-programmable gate array (“FPGA”) and controller functions are programmed into the FPGA. In a particular embodiment, the FPGA is a Xilinx® FPGA. In another embodiment, the solid-state storage controller 104 comprises components specifically designed as a solid-state storage controller 104, such as an application-specific integrated circuit (“ASIC”) or custom logic solution. Each solid-state storage controller 104 typically includes a write data pipeline 106 and a read data pipeline 108, which are describe further in relation to FIG. 3. In another embodiment, at least one solid-state storage controller 104 is made up of a combination FPGA, ASIC, and custom logic components.	91	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	FIG. 2B is a schematic block diagram illustrating one embodiment 201 of a solid-state storage device controller 202 that includes a solid-state storage device 102 in accordance with the present invention. The solid-state storage device controller 202 may include a number of solid-state storage controllers 0-N 104a-n, each controlling solid-state storage 110. In the depicted embodiment, two solid-state controllers are shown: solid-state controller 0104a and solid-state storage controller N 104n, and each controls solid-state storage 110a-n. In the depicted embodiment, solid-state storage controller 0104a controls a data channel so that the attached solid-state storage 110a stores data. Solid-state storage controller N 104n controls an index metadata channel associated with the stored data and the associated solid-state storage 110n stores index metadata. In an alternate embodiment, the solid-state storage device controller 202 includes a single solid-state controller 104a with a single solid-state storage 110a. In another embodiment, there are a plurality of solid-state storage controllers 104a-n and associated solid-state storage 110a-n. In one embodiment, one or more solid state controllers 104a-104n−1, coupled to their associated solid-state storage 110a-110n−1, control data while at least one solid-state storage controller 104n, coupled to its associated solid-state storage 110n, controls index metadata.	90	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In another embodiment, the storage controller 152 emulates block storage by accepting block objects. A block object may include one or more data blocks in a block structure. In one embodiment, the storage controller 152 treats the block object as any other object. In another embodiment, an object may represent an entire block device, partition of a block device, or some other logical or physical sub-element of a block device including a track, sector, channel, and the like. Of particular note is the ability to remap a block device RAID group to an object supporting a different RAID construction such as progressive RAID. One skilled in the art will recognize other mappings of traditional or future block devices to objects.	88	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, the storage controller 152 emulates block storage and an object communicated between the requesting device 155 and the storage controller 152 comprises one or more data blocks. In one embodiment, the requesting device 155 includes a driver so that the storage device 150 appears as a block storage device. For example, the requesting device 155 may send a block of data of a certain size along with a physical address of where the requesting device 155 wants the data block stored. The storage controller 152 receives the data block and uses the physical block address transmitted with the data block or a transformation of the physical block address as an object identifier. The storage controller 152 then stores the data block as an object or data segment of an object by packetizing the data block and storing the data block at will. The object index module 266 then creates an entry in the object index using the physical block-based object identifier and the actual physical location where the storage controller 152 stored the data packets comprising the data from the data block.	87	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, where an object request received by the object request receiver module 260 includes a write request, the storage controller 152 receives one or more data segments of an object from memory of a requesting device 155 as a local or remote direct memory access (“DMA,” “RDMA”) operation. In a preferred example, the storage controller 152 pulls data from the memory of the requesting device 155 in one or more DMA or RDMA operations. In another example, the requesting device 155 pushes the data segment(s) to the storage controller 152 in one or more DMA or RDMA operations. In another embodiment, where the object request includes a read request, the storage controller 152 transmits one or more data segments of an object to the memory of the requesting device 155 in one or more DMA or RDMA operations. In a preferred example, the storage controller 152 pushes data to the memory of the requesting device 155 in one or more DMA or RDMA operations. In another example, the requesting device 155 pulls data from the storage controller 152 in one or more DMA or RDMA operations. In another example, the storage controller 152 pulls object command request sets from the memory of the requesting device 155 in one or more DMA or RDMA operations. In another example, the requesting device 155 pushes object command request sets to the storage controller 152 in one or more DMA or RDMA operations.	86	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, the object index in volatile memory is stored periodically in a data storage device 154. In a particular example, the object index, or “index metadata,” is stored periodically in a solid-state storage 110. In another embodiment, the index metadata is stored in a solid-state storage 110n separate from solid-state storage 110a-110n-1 storing packets. The index metadata is managed independently from data and object metadata transmitted from a requesting device 155 and managed by the storage controller 152/solid-state storage device controller 202. Managing and storing index metadata separate from other data and metadata from an object allows efficient data flow without the storage controller 152/solid-state storage device controller 202 unnecessarily processing object metadata.	85	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	an ECC correction module configured to resolve an error in the ECC block read from the solid-state storage elements; and	250	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.	255	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	wherein the read data pipeline is configured to read the plurality of ECC blocks from the solid-state storage elements, wherein the ECC correction module is configured to resolve errors of each of the plurality of ECC blocks, and wherein the depacketizer is configured to access the portion of the data stream within each of the plurality of ECC blocks and is configured to reconstruct the data stream therefrom.	254	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 24.The apparatus of claim 22, wherein the packetizer is configured to generate a plurality of packets comprising the data stream, and the ECC generator is configured to generate a plurality of ECC blocks comprising the packets, and wherein the write data pipeline is configured to store the plurality ECC blocks on the solid-state storage elements, wherein at least one of the plurality of ECC blocks is stored on two or more of the solid-state storage elements, and	253	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 23.The apparatus of claim 22, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.	252	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a depacketizer configured to access the portion of the streamed data in the ECC block.	251	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	US-8380915-A1	In certain embodiments, the configuration update module 510 updates a configuration parameter in response to a change in a storage media characteristic that is greater than a predefined change threshold. The configuration update module 510, in one embodiment, updates configuration parameters in cooperation with the configuration parameter module 504, using the configuration parameter module 504, or the like. The configuration update module 510, in another embodiment, may update configuration parameters stored in a configuration parameter repository, as described in greater detail below with regard to FIGS. 8A and 8B.	264	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, the ECC is a block code that is distributed with the data. Furthermore, the data and the ECC may not align with any particular physical hardware boundary. As a result, error correction with the ECC codes is not dependent on a particular hardware configuration. Therefore, the ECC and corresponding data may form an ECC chunk 616 and the ECC chunk may be divided and stored on one or more of the N storage elements 606a-n. An ECC chunk 616 typically spans at least a portion of a plurality of physical pages 610 of a logical page where the data and ECC generated from the data 612a, 612b, . . . 612m are spread across the N storage elements 606a-n. In one embodiment, a LP includes a plurality of ECC chunks 616. A physical page 610 may contain one or more data bytes of the ECC chunk 616. An ECC chunk 616 may span multiple rows within a physical page 610 and a physical page 610 may include a plurality of ECC chunks 616.	273	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	In one embodiment, a group of PEBs (PEB 1608a-PEB m 608m) forms a logical erase block (“LEB”). An LEB spans the array of N storage elements 600. Furthermore, in an embodiment, a logical page (“LP”) spans a plurality of physical pages 610 in a row. In another embodiment a logical page spans N storage elements 606a-n.	272	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	Furthermore, in one embodiment each storage element 606 includes a physical erase block or “PEB” 608. For example, storage element one 606a includes PEB one 608a. A physical erase block is typically an erase block located on one die, chip, or other storage element 606. Each PEB 608 includes m physical pages 610. For example, PEB one 608a includes page 0610a . . . page m 614a. Each physical page 610a stores a portion of data (“D 0, D 1, . . . , D m”) 612 and ECC checkbits distributed with the data 612.	271	Added by DJM 3 2021	3/12/21, 12:00 AM
View Edit Delete	US-8380915-A1	The array 600 of storage elements 606, in one embodiment, includes N number of storage elements 606a, 606b, 606c, . . . 606n. Each storage element 606 may comprise a device, a chip, a portion of a chip, a die, or the like. In the depicted embodiment, the storage elements 606a-n form a bank 602a. The array 600, in one embodiment, includes several banks 602a . . . 602m. The banks 602a-m, in the depicted embodiment, include several channels 604a, 604b, 604c, . . . , 604n. In one embodiment, a packet or data set is written across the several channels 604a-n and data is read separately from each channel 604a-n and reassembled into the packet. In another embodiment, an ECC chunk 616, packet, or data set is written across the several channels 604a-n and data is read in parallel from all the channels 604a-n. One read operation on a bank 602a may read a whole ECC chunk 616, packet, or data set or a portion of an ECC chunk 616, packet, or data set that is reassembled into a whole ECC chunk 616, packet, or data set. In the depicted embodiment, each channel includes at least one storage element 606 in each bank 602.	270	Added by DJM 3 2021	3/12/21, 12:00 AM

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