Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US8533406B2	The apparatuses and systems disclosed herein may further comprise an index comprising mappings between logical identifiers and physical addresses on the non-volatile storage medium, wherein the marking module is configured to remove a mapping between the logical identifier and the physical addresses of the data from the index. The marking module may be further configured to delete a reference to the physical address from an index entry of the logical identifier. Removal of the mapping may indicate that data stored at the physical address can be erased from the non-volatile storage medium.	18	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	The apparatuses and systems disclosed herein may further comprise a request receiver module configured to receive the hint. The request receiver module may comprise a driver. The request receiver module may be configured to receive the hint from a file system, the file system configured to send the hint in response to deletion of file system data associated with the logical identifier and/or removal of a file associated with the logical identifier.	19	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	In some embodiments, the request receiver module is configured to receive the hint from an application, wherein the application is configured to send the hint in response to determining that data associated with the logical identifier no longer needs to be retained on the non-volatile storage medium.	20	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	The apparatuses and systems disclosed herein may further comprise a storage recovery module configured to recover the physical storage location at the physical address, and a storage module configured to store data associated with another logical identifier on the physical storage location in response to recovering the physical storage location.	21	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	The apparatuses and systems disclosed herein may comprise, an index configured to contain a plurality of entries, wherein each entry associates a logical identifier with a physical storage location of a non-volatile storage medium that comprises valid data of the logical identifier, a request receiver module configured to receive an indication that a specified logical identifier is empty, and an index module configured to remove an entry from the index that associates the specified logical identifier with a physical storage location of the non-volatile storage medium in response to the indication. The request receiver module may be configured to receive the indication through one of a block device interface and via a block storage protocol.	22	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	The apparatuses and systems disclosed herein may further comprise a storage recovery module configured to erase a storage division comprising the physical storage location in response to removing the entry.	23	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	The apparatuses and systems disclosed herein may further comprise a read request response module configured to return an indication that the logical identifier is empty in response to a request to read data of the logical identifier while the data remains on the non-volatile storage medium.	24	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	Also, because the storage controller(s) 152 operate autonomously as RAID controllers, the RAID controllers can perform progressive RAIDing and can transform objects or portions of objects striped across data storage devices 154 with one RAID level to another RAID level without the requesting device 155 being affected, participating or even detecting the change in RAID levels. In the preferred embodiment, progressing the RAID configuration from one level to another level may be accomplished autonomously on an object or even a packet bases and is initiated by a distributed RAID control module operating in one of the storage devices 150 or the storage controllers 152. Typically, RAID progression will be from a higher performance and lower efficiency storage configuration such as RAID 1 to a lower performance and higher storage efficiency configuration such as RAID5 where the transformation is dynamically initiated based on the frequency of access. But, one can see that progressing the configuration from RAID5 to RAID 1 is also possible. Other processes for initiating RAID progression may be configured or requested from clients or external agents such a storage system management server request. One of skill in the art will recognize other features and benefits of a storage device 102 with a storage controller 152 that autonomously manages objects.	71	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	In another embodiment, the object index reconstruction module 272 locates packets using packet header information along with container packet information to identify physical locations of the packets, object identifier, and sequence number of each packet to reconstruct entries in the object index. In one embodiment, erase blocks are time stamped or given a sequence number as packets are written and the timestamp or sequence information of an erase block is used along with information gathered from container headers and packet headers to reconstruct the object index. In another embodiment, timestamp or sequence information is written to an erase block when the erase block is recovered. After recovery, logical erase blocks may be added to a queue. Logical erase blocks may be selected for use from the queue based on the sequence information marked thereon. Accordingly, the temporal order of data stored on the logical erase blocks may be determined by the sequence information marked on the storage divisions, making it possible to track messages that span logical storage divisions.	91	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	In one embodiment, the object index in volatile memory is stored periodically in a data storage device 154. In a particular example, the object index, or “index metadata,” is stored periodically in a solid-state storage 110. In another embodiment, the index metadata is stored in a solid-state storage 110n separate from solid-state storage 110a-110n−1 storing packets. The index metadata is managed independently from data and object metadata transmitted from a requesting device 155 and managed by the storage controller 152/solid-state storage device controller 202. Managing and storing index metadata separate from other data and metadata from an object allows efficient data flow without the storage controller 152/solid-state storage device controller 202 unnecessarily processing object metadata.	93	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	FIG. 2B is a schematic block diagram illustrating one embodiment 201 of a solid-state storage device controller 202 that includes a write data pipeline 106 and a read data pipeline 108 in a solid-state storage device 102 in accordance with the present invention. The solid-state storage device controller 202 may include a number of solid-state storage controllers 0-N 104a-n, each controlling solid-state storage 110. In the depicted embodiment, two solid-state controllers are shown: solid-state controller 0104a and solid-state storage controller N 104n, and each controls solid-state storage 110a-n. In the depicted embodiment, solid-state storage controller 0104a controls a data channel so that the attached solid-state storage 110a stores data. Solid-state storage controller N 104n controls an index metadata channel associated with the stored data and the associated solid-state storage 110n stores index metadata. In an alternate embodiment, the solid-state storage device controller 202 includes a single solid-state controller 104a with a single solid-state storage 110a. In another embodiment, there are a plurality of solid-state storage controllers 104a-n and associated solid-state storage 110a-n. In one embodiment, one or more solid state controllers 104a-104n−1, coupled to their associated solid-state storage 110a-110n−1, control data while at least one solid-state storage controller 104n, coupled to its associated solid-state storage 110n, controls index metadata.	98	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	A solid-state storage element (e.g. SSS 0.0 216a) is typically configured as a chip (a package of one or more dies) or a die on a circuit board. As depicted, a solid-state storage element (e.g. 216a) operates independently or semi-independently of other solid-state storage elements (e.g. 218a) even if these several elements are packaged together in a chip package, a stack of chip packages, or some other package element. As depicted, a column of solid-state storage elements 216, 218, 220 is designated as a bank 214. As depicted, there may be “n” banks 214a-n and “m” solid-state storage elements 216a-m, 218a-m, 220a-m per bank in an array of n×m solid-state storage elements 216, 218, 220 in a solid-state storage 110. In one embodiment, a solid-state storage 110a includes twenty solid-state storage elements 216, 218, 220 per bank 214 with eight banks 214 and a solid-state storage 110n includes 2 solid-state storage elements 216, 218 per bank 214 with one bank 214. In one embodiment, each solid-state storage element 216, 218, 220 is comprised of a single-level cell (“SLC”) devices. In another embodiment, each solid-state storage element 216, 218, 220 is comprised of multi-level cell (“MLC”) devices.	102	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	In one embodiment, solid-state storage elements for multiple banks that share a common storage I/O bus 210a row (e.g. 216b, 218b, 220b) are packaged together. In one embodiment, a solid-state storage element 216, 218, 220 may have one or more dies per chip with one or more chips stacked vertically and each die may be accessed independently. In another embodiment, a solid-state storage element (e.g. SSS 0.0 216a) may have one or more virtual dies per die and one or more dies per chip and one or more chips stacked vertically and each virtual die may be accessed independently. In another embodiment, a solid-state storage element SSS 0.0 216a may have one or more virtual dies per die and one or more dies per chip with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.	103	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	Typically, when a packet is written to a particular location within a solid-state storage element 216, 218, 220, wherein the packet is intended to be written to a location within a particular page which is specific to a of a particular erase block of a particular element of a particular bank, a physical address is sent on the storage I/O bus 210 and followed by the packet. The physical address contains enough information for the solid-state storage element 216, 218, 220 to direct the packet to the designated location within the page. Since all storage elements in a row of storage elements (e.g. SSS 0.0-SSS0.N 216a, 218a, 220a) are accessed simultaneously by the appropriate bus within the storage I/O bus 210a.a, to reach the proper page and to avoid writing the data packet to similarly addressed pages in the row of storage elements (SSS 0.0-SSS0.N 216a, 218a, 220a), the bank 214a that includes the solid-state storage element SSS 0.0 216a with the correct page where the data packet is to be written is simultaneously selected by the storage control bus 212.	109	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	Typically the data is transferred from the local bus 206 to one or more data buffers 222 as directed by the master controller 224 and the buffer controller 208. The data then flows out of the buffer(s) 222 to the data bus 204, through a solid-state controller 104, and on to the solid-state storage 110 such as NAND flash or other storage media. In a preferred embodiment, data and associated out-of-band metadata (“object metadata”) arriving with the data is communicated using one or more data channels comprising one or more solid-state storage controllers 104a-104n−1 and associated solid-state storage 110a-110n−1 while at least one channel (solid-state storage controller 104n, solid-state storage 110n) is dedicated to in-band metadata, such as index information and other metadata generated internally to the solid-state storage device 102.	120	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	In one embodiment, the solid-state controller 104 includes one bank interleave controller 344 that serves all of the storage elements 216, 218, 220 of the solid-state storage 110. In another embodiment, the solid-state controller 104 includes a bank interleave controller 344 for each row of storage elements 216a-m, 218a-m, 220a-m. For example, one bank interleave controller 344 serves one row of storage elements SSS 0.0-SSS 0.N 216a, 218a, 220a, a second bank interleave controller 344 serves a second row of storage elements SSS1.0-SSS1.N 216b, 218b, 220b, etc.	197	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	In the preferred embodiment, the solid-state storage controller 104 includes a MUX 350 for each row of solid-state storage elements (e.g. SSS 0.1 216a, SSS 0.2 218a, SSS0.N 220a). A MUX 350 combines data from the write data pipeline 106 and commands sent to the solid-state storage 110 via the storage I/O bus 210 and separates data to be processed by the read data pipeline 108 from commands. Packets stored in the write buffer 320 are directed on busses out of the write buffer 320 through a write synchronization buffer 308 for each row of solid-state storage elements (SSS x.0 to SSS x.N 216, 218, 220) to the MUX 350 for each row of solid-state storage elements (SSS x.0 to SSS x.N 216, 218, 220). The commands and read data are received by the MUXes 350 from the storage I/O bus 210. The MUXes 350 also direct status messages to the storage bus controller 348.	204	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	The storage bus controller 348 includes a mapping module 424. The mapping module 424 maps a logical address of an erase block to one or more physical addresses of an erase block. For example, a solid-state storage 110 with an array of twenty storage elements (e.g. SSS 0.0 to SSS M.0 216) per block 214a may have a logical address for a particular erase block mapped to twenty physical addresses of the erase block, one physical address per storage element. Because the storage elements are accessed in parallel, erase blocks at the same position in each storage element in a row of storage elements 216a, 218a, 220a will share a physical address. To select one erase block (e.g. in storage element SSS 0.0 216a) instead of all erase blocks in the row (e.g. in storage elements SSS 0.0, 0.1, . . . 0.N 216a, 218a, 220a), one bank (in this case bank-0214a) is selected.	205	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	This logical-to-physical mapping for erase blocks is beneficial because if one erase block becomes damaged or inaccessible, the mapping can be changed to map to another erase block. This mitigates the loss of losing an entire virtual erase block when one element's erase block is faulty. The remapping module 430 changes a mapping of a logical address of an erase block to one or more physical addresses of a virtual erase block (spread over the array of storage elements). For example, virtual erase block 1 may be mapped to erase block 1 of storage element SSS 0.0 216a, to erase block 1 of storage element SSS1.0 216b, . . . , and to storage element M.0 216m, virtual erase block 2 may be mapped to erase block 2 of storage element SSS 0.1 218a, to erase block 2 of storage element SSS1.1 218b, . . . , and to storage element M.1 218m, etc.	206	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US8533406B2	If erase block 1 of a storage element SSS0.0 216a is damaged, experiencing errors due to wear, etc., or cannot be used for some reason, the remapping module 430 could change the logical-to-physical mapping for the logical address that pointed to erase block 1 of virtual erase block 1. If a spare erase block (call it erase block 221) of storage element SSS 0.0 216a is available and currently not mapped, the remapping module 430 could change the mapping of virtual erase block 1 to point to erase block 221 of storage element SSS 0.0 216a, while continuing to point to erase block 1 of storage element SSS1.0 216b, erase block 1 of storage element SSS 2.0 (not shown) . . . , and to storage element M.0 216m. The mapping module 424 or remapping module 430 could map erase blocks in a prescribed order (virtual erase block 1 to erase block 1 of the storage elements, virtual erase block 2 to erase block 2 of the storage elements, etc.) or may map erase blocks of the storage elements 216, 218, 220 in another order based on some other criteria.	207	Added by DJM 3 2021	3/24/21, 12:00 AM

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