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Typically, when a packet is written to a particular location within a solid-state storage element 216, 218, 220, wherein the packet is intended to be written to a location within a particular page which is specific to a of a particular erase block of a particular element of a particular bank, a physical address is sent on the storage I/O bus 210 and followed by the packet. The physical address contains enough information for the solid-state storage element 216, 218, 220 to direct the packet to the designated location within the page. Since all storage elements in a row of storage elements (e.g. SSS 0.0-SSS0.N 216a, 218a, 220a) are accessed simultaneously by the appropriate bus within the storage I/O bus 210a.a, to reach the proper page and to avoid writing the data packet to similarly addressed pages in the row of storage elements (SSS 0.0-SSS0.N 216a, 218a, 220a), the bank 214a that includes the solid-state storage element SSS 0.0 216a with the correct page where the data packet is to be written is simultaneously selected by the storage control bus 212.

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<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">Typically, when a packet is written to a particular location within a solid-state storage element </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t xml:space="preserve">, wherein the packet is intended to be written to a location within a particular page which is specific to a of a particular erase block of a particular element of a particular bank, a physical address is sent on the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> and followed by the packet. The physical address contains enough information for the solid-state storage element </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t xml:space="preserve"> to direct the packet to the designated location within the page. Since all storage elements in a row of storage elements (e.g. SSS 0.0-SSS0.N </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">) are accessed simultaneously by the appropriate bus within the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t>a.a</w:t></w:r><w:r><w:t xml:space="preserve">, to reach the proper page and to avoid writing the data packet to similarly addressed pages in the row of storage elements (SSS 0.0-SSS0.N </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">), the bank </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">that includes the solid-state storage element SSS 0.0 </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">with the correct page where the data packet is to be written is simultaneously selected by the storage control bus </w:t></w:r><w:r><w:t>212</w:t></w:r><w:r><w:t>.</w:t></w:r></w:p>