Paragraph 103
Paragraph 103
Matter Number
US8533406B2
Paragraph Number
103
Application Number
—
Reference Case 1
US8533406B2
Reference Case 2
—
Created
3/24/21, 12:00 AM
Modified
3/24/21, 12:00 AM
Id
3,596
Content
In one embodiment, solid-state storage elements for multiple banks that share a common storage I/O bus 210a row (e.g. 216b, 218b, 220b) are packaged together. In one embodiment, a solid-state storage element 216, 218, 220 may have one or more dies per chip with one or more chips stacked vertically and each die may be accessed independently. In another embodiment, a solid-state storage element (e.g. SSS 0.0 216a) may have one or more virtual dies per die and one or more dies per chip and one or more chips stacked vertically and each virtual die may be accessed independently. In another embodiment, a solid-state storage element SSS 0.0 216a may have one or more virtual dies per die and one or more dies per chip with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.
Notes
Added by DJM 3 2021