Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	2380.2.01	If erase block 1 of a storage element SSS0.0216a is damaged, experiencing errors due to wear, etc., or cannot be used for some reason, the remapping module 430 could change the logical-to-physical mapping for the logical address that pointed to erase block 1 of virtual erase block 1. If a spare erase block (call it erase block 221) of storage element SSS 0.0216a is available and currently not mapped, the remapping module 430 could change the mapping of virtual erase block 1 to point to erase block 221 of storage element SSS 0.0216a, while continuing to point to erase block 1 of storage element SSS 1.0216b, erase block 1 of storage element SSS 2.0 (not shown) . . . , and to storage element M.0216m. The mapping module 424 or remapping module 430 could map erase blocks in a prescribed order (virtual erase block 1 to erase block 1 of the storage elements, virtual erase block 2 to erase block 2 of the storage elements, etc.) or may map erase blocks of the storage elements 216, 218, 220 in another order based on some other criteria.	199	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	This logical-to-physical mapping for erase blocks is beneficial because if one erase block becomes damaged or inaccessible, the mapping can be changed to map to another erase block. This mitigates the loss of losing an entire virtual erase block when one element's erase block is faulty. The remapping module 430 changes a mapping of a logical address of an erase block to one or more physical addresses of a virtual erase block (spread over the array of storage elements). For example, virtual erase block 1 may be mapped to erase block 1 of storage element SSS 0.0216a, to erase block 1 of storage element SSS 1.0216b, . . . , and to storage element M.0216m, virtual erase block 2 may be mapped to erase block 2 of storage element SSS 0.1218a, to erase block 2 of storage element SSS 1.1218b, . . . , and to storage element M.1218m, etc.	198	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The storage bus controller 348 includes a mapping module 424. The mapping module 424 maps a logical address of an erase block to one or more physical addresses of an erase block. For example, a solid-state storage 110 with an array of twenty storage elements (e.g. SSS 0.0 to SSS M.0216) per block 214a may have a logical address for a particular erase block mapped to twenty physical addresses of the erase block, one physical address per storage element. Because the storage elements are accessed in parallel, erase blocks at the same position in each storage element in a row of storage elements 216a, 218a, 220a will share a physical address. To select one erase block (e.g. in storage element SSS 0.0216a) instead of all erase blocks in the row (e.g. in storage elements SSS 0.0, 0.1, . . . 0.N 216a, 218a, 220a), one bank (in this case bank-0214a) is selected.	197	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The ECC generator 304 receives a packet from the packetizer 302 and generates 508 ECC for the data packets. Typically, there is no fixed relationship between packets and ECC blocks. An ECC block may comprise one or more packets. A packet may comprise one or more ECC blocks. A packet may start and end anywhere within an ECC block. A packet may start anywhere in a first ECC block and end anywhere in a subsequent ECC block.	205	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In the preferred embodiment, the solid-state storage controller 104 includes a MUX 350 that comprises an array of multiplexers 350a-n where each multiplexer is dedicated to a row in the solid-state storage array 110. For example, multiplexer 350a is associated with solid-state storage elements 216a, 218a, 220a. MUX 350 routes the data from the write data pipeline 106 and commands from the storage bus controller 348 to the solid-state storage 110 via the storage I/O bus 210 and routes data and status messages from the solid-state storage 110 via the storage I/O bus 210 to the read data pipeline 108 and the control and status registers 340 through the storage bus controller 348, synchronization buffer 346, and bank interleave controller 344.	195	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The solid-state storage controller 104 includes a storage bus controller 348 that interprets and translates commands for data sent to and read from the solid-state storage 110 and status messages received from the solid-state storage 110 based on the type of solid-state storage 110. For example, the storage bus controller 348 may have different timing requirements for different types of storage, storage with different performance characteristics, storage from different manufacturers, etc. The storage bus controller 348 also sends control commands to the storage control bus 212.	194	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The solid-state storage controller 104 includes a synchronization buffer 346 that buffers commands and status messages sent and received from the solid-state storage 110. The synchronization buffer 346 is located at the boundary between the solid-state storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences. The synchronization buffer 346, write synchronization buffer 308, and read synchronization buffer 328 may be independent or may act together to buffer data, commands, status messages, etc. In the preferred embodiment, the synchronization buffer 346 is located where there are the fewest number of signals crossing the clock domains. One skilled in the art will recognize that synchronization between clock domains may be arbitrarily moved to other locations within the solid-state storage device 102 in order to optimize some aspect of design implementation.	193	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Storage-Specific Components	192	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In another alternate embodiment (not shown), commands are stored in a single queue where the commands may be pulled from the queue in an order other than how they are stored so that the bank interleave controller 344 can execute a command on one bank 214a while other commands are executing on the remaining banks 214b-n. One of skill in the art will easily recognize other queue configurations and types to enable execution of a command on one bank 214a while other commands are executing on other banks 214b-n.	191	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	FIG. 4B is a schematic block diagram illustrating an alternate embodiment 401 of a bank interleave controller 344 in the solid-state storage controller 104 in accordance with the present invention. The components 210, 212, 340, 346, 348, 350, 402-430 depicted in the embodiment shown in FIG. 4B are substantially similar to the bank interleave apparatus 400 described in relation to FIG. 4A except that each bank 214 includes a single queue 432a-n and the read commands, write commands, erase commands, management commands, etc. for a bank (e.g. Bank-0214a) are directed to a single queue 432a for the bank 214a. The queues 432, in one embodiment, are FIFO. In another embodiment, the queues 432 can have commands pulled from the queues 432 in an order other than the order they were stored. In another alternate embodiment (not shown), the read agent 402, write agent 404, erase agent 406, and management agent 408 may be combined into a single agent assigning commands to the appropriate queues 432a-n.	190	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, the solid-state controller 104 includes one bank interleave controller 344 that serves all of the storage elements 216, 218, 220 of the solid-state storage 110. In another embodiment, the solid-state controller 104 includes a bank interleave controller 344 for each row of storage elements 216a-m, 218a-m, 220a-m. For example, one bank interleave controller 344 serves one row of storage elements SSS 0.0-SSS 0.N 216a, 218a, 220a, a second bank interleave controller 344 serves a second row of storage elements SSS 1.0-SSS 1.N 216b, 218b, 220b, etc.	189	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	receiving, at a write data pipeline, data to be stored on the solid-state storage device, the write data pipeline communicatively coupled to the two or more solid-state storage elements;	213	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 7.The method of claim 1, wherein the error-correcting code length is predetermined based on one of a performance metric, an efficiency metric, and a data integrity metric.	221	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 6.The method of claim 1, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.	220	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 5.The method of claim 1, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a block size of the received data.	219	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 4.The method of claim 1, wherein the first portion of the ECC block comprises a portion of the received data and the second portion of the ECC block comprises the error-correcting code capable of correcting an error in the portion of the received data.	218	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 3.The method of claim 1, wherein storing a first portion further comprises storing the first portion and the second portion on the first and the second solid-state storage elements responsive to a single solid-state storage element programming command.	217	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 2.The method of claim 1, wherein storing the ECC block comprises storing the first portion of the ECC block on a page of the first solid-state storage element and the second portion of the ECC block on a page of the second solid-state storage element.	216	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	storing a first portion of the ECC block on a page of a first one of the solid-state storage elements and a second portion of the ECC block on a page of a second one of the solid-state storage elements.	215	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	generating an error-correcting code (ECC) block comprising at least a portion of the received data and an error-correcting code capable of correcting an error in the ECC block; and	214	Added by DJM 3 2021	3/16/21, 12:00 AM

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