Paragraph 193
Paragraph 193
Matter Number
2380.2.01
Paragraph Number
193
Application Number
11952091
Reference Case 1
2380.2.01
Reference Case 2
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Created
3/16/21, 12:00 AM
Modified
3/16/21, 12:00 AM
Id
3,106
Content
The solid-state storage controller 104 includes a synchronization buffer 346 that buffers commands and status messages sent and received from the solid-state storage 110. The synchronization buffer 346 is located at the boundary between the solid-state storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences. The synchronization buffer 346, write synchronization buffer 308, and read synchronization buffer 328 may be independent or may act together to buffer data, commands, status messages, etc. In the preferred embodiment, the synchronization buffer 346 is located where there are the fewest number of signals crossing the clock domains. One skilled in the art will recognize that synchronization between clock domains may be arbitrarily moved to other locations within the solid-state storage device 102 in order to optimize some aspect of design implementation.
Notes
Added by DJM 3 2021