Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Application	Content	Paragraph Number	Notes	Modified
		Content		Paragraph Number	Notes	Any Field
View Edit Delete	2380.2.01	Claim 24.The apparatus of claim 22, wherein the packetizer is configured to generate a plurality of packets comprising the data stream, and the ECC generator is configured to generate a plurality of ECC blocks comprising the packets, and wherein the write data pipeline is configured to store the plurality ECC blocks on the solid-state storage elements, wherein at least one of the plurality of ECC blocks is stored on two or more of the solid-state storage elements, and	253	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 23.The apparatus of claim 22, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.	252	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a depacketizer configured to access the portion of the streamed data in the ECC block.	251	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	an ECC correction module configured to resolve an error in the ECC block read from the solid-state storage elements; and	250	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a read data pipeline configured to read the ECC block from the solid-state storage elements, wherein reading the ECC block comprises reading the first portion of the ECC block from the first solid-state storage element and the second portion from the second solid-state storage element, the read data pipeline comprising,	249	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	wherein the write data pipeline is configured to store a first portion of the ECC block on a first one of the solid-state storage elements and a second portion of the ECC block on a second one of the solid-state storage elements; and	248	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 8.The method of claim 1, further comprising packetizing the received data into one or more packets, wherein the ECC block comprises at least a portion of at least one of the packets and the ECC block having no fixed relationship between a size of the packets and a size of the ECC block.	222	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a packetizer configured to packetize a stream of data into one or more packets, each packet comprising at least a portion of the data stream;	246	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a write data pipeline comprising,	245	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a solid-state storage controller communicatively coupled to the two or more solid-state storage elements and comprising,	244	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	a solid-state storage device comprising two or more solid-state storage elements; and	243	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 22.An apparatus to manage data in a solid-state storage device, comprising:	242	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 21.The computer program product of claim 18, wherein each solid-state storage element comprises a plurality of erase blocks, the operations further comprising generating a plurality of ECC blocks, wherein the ECC blocks divide evenly within the erase blocks.	241	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 20.The computer program product of claim 18, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.	240	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In the preferred embodiment, the solid-state storage controller 104 includes a MUX 350 for each row of solid-state storage elements (e.g. SSS 0.1216a, SSS 0.2218a, SSS 0.N 220a). A MUX 350 combines data from the write data pipeline 106 and commands sent to the solid-state storage 110 via the storage I/O bus 210 and separates data to be processed by the read data pipeline 108 from commands. Packets stored in the write buffer 320 are directed on busses out of the write buffer 320 through a write synchronization buffer 308 for each row of solid-state storage elements (SSS x.0 to SSS x.N 216, 218, 220) to the MUX 350 for each row of solid-state storage elements (SSS x.0 to SSS x.N 216, 218, 220). The commands and read data are received by the MUXes 350 from the storage I/O bus 210. The MUXes 350 also direct status messages to the storage bus controller 348.	196	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Typically, a first packet includes an object identifier that identifies the object for which the packet was created. A second packet may include a header with information used by the solid-state storage device 102 to associate the second packet to the object identified in the first packet and offset information locating the second packet within the object, and data. The solid-state storage device controller 202 manages the bank 214 and physical area to which the packets are streamed.	204	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	FIG. 5 is a schematic flow chart diagram illustrating one embodiment of a method 500 for managing data in a solid-state storage device 102 using a data pipeline in accordance with the present invention. The method 500 begins 502 and the input buffer 306 receives 504 one or more data segments to be written to the solid-state storage 110. The one or more data segments typically include at least a portion of an object but may be an entire object. The packetizer 302 may create one or more object specific packets in conjunction with an object. The packetizer 302 adds a header to each packet which typically includes the length of the packet and a sequence number for the packet within the object. The packetizer 302 receives 504 the one or more data or metadata segments that were stored in the input buffer 306 and packetizes 506 the one or more data or metadata segments by creating one or more packets sized for the solid-state storage 110 where each packet includes one header and data from the one or more segments.	203	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Flow Charts	202	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, the storage bus controller 348 includes a status capture module 426 that receives status messages from the solid-state storage 110 and sends the status messages to the status MUX 422. In another embodiment, when the solid-state storage 110 is flash memory, the storage bus controller 348 includes a NAND bus controller 428. The NAND bus controller 428 directs commands from the read and write data pipelines 106, 108 to the correct location in the solid-state storage 110, coordinates timing of command execution based on characteristics of the flash memory, etc. If the solid-state storage 110 is another solid-state storage type, the NAND bus controller 428 would be replaced by a bus controller specific to the storage type. One of skill in the art will recognize other functions of a NAND bus controller 428.	201	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In one embodiment, the erase blocks could be grouped by access time. Grouping by access time, meaning time to execute a command, such as programming (writing) data into pages of specific erase blocks, can level command completion so that a command executed across the erase blocks of a virtual erase block is not limited by the slowest erase block. In other embodiments, the erase blocks may be grouped by wear level, health, etc. One of skill in the art will recognize other factors to consider when mapping or remapping erase blocks.	200	Added by DJM 3 2021	3/16/21, 12:00 AM

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