Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	2380.2.01	Claim 21.The computer program product of claim 18, wherein each solid-state storage element comprises a plurality of erase blocks, the operations further comprising generating a plurality of ECC blocks, wherein the ECC blocks divide evenly within the erase blocks.	241	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 20.The computer program product of claim 18, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.	240	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 19.The computer program product of claim 18, wherein the first portion of the ECC block comprises a portion of the one or more packets and the second portion of the ECC block comprises the error-correcting code capable of correcting an error in the portion of the one or more packets.	239	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Typically, a first packet includes an object identifier that identifies the object for which the packet was created. A second packet may include a header with information used by the solid-state storage device 102 to associate the second packet to the object identified in the first packet and offset information locating the second packet within the object, and data. The solid-state storage device controller 202 manages the bank 214 and physical area to which the packets are streamed.	204	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	generating an error-correcting code (ECC) block comprising at least a portion of one or more of the packets and an error-correcting code configured to correct an error in the ECC block, the ECC block having no fixed relationship between a size of the packets and a size of the ECC block; and	237	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	packetizing a stream of data into one or more packets, each packet comprising at least a portion of the data stream;	236	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 18.A computer program product stored on a non-transitory computer readable medium having computer usable program code executable to perform operations of storing data on a solid-state storage device comprising two or more solid-state storage elements, each solid-state storage element partitioned into a plurality of pages, the operations comprising:	235	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 17.The solid-state storage device of claim 10, wherein each solid-state storage element comprises a plurality of erase blocks, and wherein the ECC generator is configured to generate a plurality of ECC blocks configured to divide evenly within the erase blocks.	234	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 16.The solid-state storage device of claim 10, wherein the write data pipeline comprises a packetizer configured to packetize the received data into one or more packets, wherein the ECC block comprises at least a portion of at least one of the packets, and the ECC block having no fixed relationship between a size of the packets and a size of the ECC block.	233	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 15.The solid-state storage device of claim 10, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.	232	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 14.The solid-state storage device of claim 10, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a block size of the received data.	231	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 13.The solid-state storage device of claim 10, wherein the first portion of the ECC block comprises a portion of the received data and the second portion of the ECC block comprises the error-correcting code capable of correcting an error in the portion of the received data.	230	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 12.The solid-state storage device of claim 10, wherein the write data pipeline accesses the first and the second solid-state storage elements in parallel via a bus.	229	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	Claim 11.The solid-state storage device of claim 10, wherein the first portion and the second portion are stored on the first and the second solid-state storage elements responsive to a single solid-state storage element page programming command.	228	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The solid-state storage controller 104 includes control and status registers 340 and corresponding control queues 342. The control and status registers 340 and control queues 342 facilitate control and sequencing commands and subcommands associated with data processed in the write and read data pipelines 106, 108. For example, a data segment in the packetizer 302 may have one or more corresponding control commands or instructions in a control queue 342 associated with the ECC generator 304. As the data segment is packetized, some of the instructions or commands may be executed within the packetizer 302. Other commands or instructions may be passed to the next control queue 342 through the control and status registers 340 as the newly formed data packet created from the data segment is passed to the next stage.	169	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The bank controllers 418 typically receive commands from the queues 410, 412, 414, 416 and generate appropriate subcommands. For example, the bank-0 write queue 412a may receive a command to write a page of data packets to bank-0214a. The bank-0 controller 418a may receive the write command at an appropriate time and may generate one or more write subcommands for each data packet stored in the write buffer 320 to be written to the page in bank-0214a. For example, bank-0 controller 418a may generate commands to validate the status of bank 0214a and the solid-state storage array 216, select the appropriate location for writing one or more data packets, clear the input buffers within the solid-state storage memory array 216, transfer the one or more data packets to the input buffers, program the input buffers into the selected location, verify that the data was correctly programmed, and if program failures occur do one or more of interrupting the master controller 224, retrying the write to the same physical location, and retrying the write to a different physical location. Additionally, in conjunction with example write command, the storage bus controller 348 will cause the one or more commands to multiplied to each of the each of the storage I/O buses 210a-n with the logical address of the command mapped to a first physical addresses for storage I/O bus 210a, and mapped to a second physical address for storage I/O bus 210b, and so forth as further described below.	181	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The queues 410, 412, 414, 416 typically receive commands and store the commands until required to be sent to the solid-state storage banks 214. In a typical embodiment, the queues 410, 412, 414, 416 are first-in, first-out (“FIFO”) registers or a U similar component that operates as a FIFO. In another embodiment, the queues 410, 412, 414, 416 store commands in an order that matches data, order of importance, or other criteria.	180	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The agents 402, 404, 406, 408 typically also monitor status of the queues 410, 412, 414, 416 and send status, interrupt, or other messages when the queues 410, 412, 414, 416 are full, nearly full, non-functional, etc. In one embodiment, the agents 402, 404, 406, 408 receive commands and generate corresponding sub-commands. In one embodiment, the agents 402, 404, 406, 408 receive commands through the control & status registers 340 and generate corresponding sub-commands which are forwarded to the queues 410, 412, 414, 416. One of skill in the art will recognize other functions of the agents 402, 404, 406, 408.	179	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	The agents 402, 404, 406, 408, in one embodiment, direct commands of the appropriate type destined for a particular bank 214a to the correct queue for the bank 214a. For example, the read agent 402 may receive a read command for bank-1214b and directs the read command to the bank-1 read queue 410b. The write agent 404 may receive a write command to write data to a location in bank-0214a of the solid-state storage 110 and will then send the write command to the bank-0 write queue 412a. Similarly, the erase agent 406 may receive an erase command to erase an erase block in bank-1214b and will then pass the erase command to the bank-1 erase queue 414b. The management agent 408 typically receives management commands, status requests, and the like, such as a reset command or a request to read a configuration register of a bank 214, such as bank-0214a. The management agent 408 sends the management command to the bank-0 management queue 416a.	178	Added by DJM 3 2021	3/16/21, 12:00 AM
View Edit Delete	2380.2.01	In the embodiment depicted in FIG. 4A, the bank interleave controller 344 includes, for each bank 214, a read queue 410 for reading data from the solid-state storage 110, a write queue 412 for write commands to the solid-state storage 110, an erase queue 414 for erasing an erase block in the solid-state storage, an a management queue 416 for management commands. The bank interleave controller 344 also includes corresponding read, write, erase, and management agents 402, 404, 406, 408. In another embodiment, the control and status registers 340 and control queues 342 or similar components queue commands for data sent to the banks 214 of the solid-state storage 110 without a bank interleave controller 344.	177	Added by DJM 3 2021	3/16/21, 12:00 AM

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