13189402

Paragraph Number

283

FIG. 6C shows that the value “11” is associated with the lowest read voltage state (labeled L0, an “erase” state), the value “01” is associated with the next lowest read voltage state (labeled L1), the value “00” is associated with the next highest read voltage state (labeled L2), and the value “10” is associated with the highest read voltage state (labeled L3). In FIG. 6C, the lowest read voltage state L0 is depicted as a negative voltage. Values, magnitudes, sizes, and the like of read voltages may vary by manufacturer and type of solid-state storage cell, each of which are encompassed by the present invention. The configuration parameters 662, in the depicted embodiment, are read voltage thresholds 662 that separate states L0, L1, L2, and L3, as described above. The solid-state storage controller 104 interprets the four discrete levels of voltage stored in the multi-level storage cell as representing two binary bits one represented by a most significant bit (MSB) in the cell encoding and one represented by a least significant bit (LSB) in the cell encoding. As explained above, other programming and encoding models may be used. Also, certain solid-state storage media 110 may have more than four possible states, allowing more than two binary values to be stored in a single multi-level storage cell. The voltage levels L0, L1, L2, and L3 may or may not be contiguous; for example, in certain embodiments, the voltage levels are separated by band gaps known as guard band. For example, L0 and L1 may be separated by 0.3V.

Added by DJM 3 2021