Dave's Patent Content Factory
Applications
Terms
Paragraphs
Claims
Docket
Logout
About
Paragraph #2,856
Edit Paragraph
View
List Paragraphs
Delete
Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
283
Application Number
13189402
Reference Case 1
Reference Case 2
Content
FIG. 6C shows that the value “11” is associated with the lowest read voltage state (labeled L0, an “erase” state), the value “01” is associated with the next lowest read voltage state (labeled L1), the value “00” is associated with the next highest read voltage state (labeled L2), and the value “10” is associated with the highest read voltage state (labeled L3). In FIG. 6C, the lowest read voltage state L0 is depicted as a negative voltage. Values, magnitudes, sizes, and the like of read voltages may vary by manufacturer and type of solid-state storage cell, each of which are encompassed by the present invention. The configuration parameters 662, in the depicted embodiment, are read voltage thresholds 662 that separate states L0, L1, L2, and L3, as described above. The solid-state storage controller 104 interprets the four discrete levels of voltage stored in the multi-level storage cell as representing two binary bits one represented by a most significant bit (MSB) in the cell encoding and one represented by a least significant bit (LSB) in the cell encoding. As explained above, other programming and encoding models may be used. Also, certain solid-state storage media 110 may have more than four possible states, allowing more than two binary values to be stored in a single multi-level storage cell. The voltage levels L0, L1, L2, and L3 may or may not be contiguous; for example, in certain embodiments, the voltage levels are separated by band gaps known as guard band. For example, L0 and L1 may be separated by 0.3V.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t>FIG. 6C</w:t></w:r><w:r><w:t xml:space="preserve"> shows that the value “11” is associated with the lowest read voltage state (labeled L</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>, an “erase” state), the value “01” is associated with the next lowest read voltage state (labeled L</w:t></w:r><w:r><w:t>1</w:t></w:r><w:r><w:t>), the value “00” is associated with the next highest read voltage state (labeled L</w:t></w:r><w:r><w:t>2</w:t></w:r><w:r><w:t>), and the value “10” is associated with the highest read voltage state (labeled L</w:t></w:r><w:r><w:t>3</w:t></w:r><w:r><w:t xml:space="preserve">). In </w:t></w:r><w:r><w:t>FIG. 6C</w:t></w:r><w:r><w:t>, the lowest read voltage state L</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t xml:space="preserve"> is depicted as a negative voltage. Values, magnitudes, sizes, and the like of read voltages may vary by manufacturer and type of solid-state storage cell, each of which are encompassed by the present invention. The configuration parameters </w:t></w:r><w:r><w:t>662</w:t></w:r><w:r><w:t xml:space="preserve">, in the depicted embodiment, are read voltage thresholds </w:t></w:r><w:r><w:t>662</w:t></w:r><w:r><w:t xml:space="preserve"> that separate states L</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>, L</w:t></w:r><w:r><w:t>1</w:t></w:r><w:r><w:t>, L</w:t></w:r><w:r><w:t>2</w:t></w:r><w:r><w:t>, and L</w:t></w:r><w:r><w:t>3</w:t></w:r><w:r><w:t xml:space="preserve">, as described above. The solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> interprets the four discrete levels of voltage stored in the multi-level storage cell as representing two binary bits one represented by a most significant bit (MSB) in the cell encoding and one represented by a least significant bit (LSB) in the cell encoding. As explained above, other programming and encoding models may be used. Also, certain solid-state storage media </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> may have more than four possible states, allowing more than two binary values to be stored in a single multi-level storage cell. The voltage levels L</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>, L</w:t></w:r><w:r><w:t>1</w:t></w:r><w:r><w:t>, L</w:t></w:r><w:r><w:t>2</w:t></w:r><w:r><w:t>, and L</w:t></w:r><w:r><w:t>3</w:t></w:r><w:r><w:t xml:space="preserve"> may or may not be contiguous; for example, in certain embodiments, the voltage levels are separated by band gaps known as guard band. For example, L</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t xml:space="preserve"> and L</w:t></w:r><w:r><w:t>1</w:t></w:r><w:r><w:t xml:space="preserve"> may be separated by 0.3V.</w:t></w:r></w:p>
Submit