13189402

Paragraph Number

281

FIG. 6B is a schematic block diagram illustrating one embodiment of an array 650 of N storage elements 606 in accordance with the present invention. The array 650, in the depicted embodiment, is substantially similar to the array 600 of FIG. 6A, but with the ECC chunk 652 including data 612a in a single storage element 606a, instead of across several storage elements 606a-n. In one embodiment, ECC checkbits for the ECC chunk 652 are stored in the single storage element 606a. Because each storage element 606a-n or channel 604a-n has separate ECC checkbits, in one embodiment, the ECC module 412 uses the separate ECC checkbits to determine in which storage elements 606a-n or channels 604a-n an error has occurred, and the configuration module 352 adjusts the read voltage thresholds of the particular storage element(s) 606 determined by the ECC module 412.

Added by DJM 3 2021