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Term #1,857
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phase-locked-loop (PLL)
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2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
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US-10637533-B2
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US-9159419-A1
US-9208071-A1
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US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
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US20100023800A1
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OPT-9
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GTS-3DES
FLO-4
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KMN-1PROV
PAT-2
PER-8 PROV
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INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
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IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
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Placeholder App
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US10318495
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PON-1PROV, 2PROV, 3PROV
PER-33
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PER-24
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71212.157.USU1
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PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
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TEST-002
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ZED006
FSP1011
GAV-PAT-1-PROV
App Docket
Created Date
Full Desc
"Phase-locked-loop" is logic that generates an output signal whose phase is related to the phase of an input signal. One example of a phase-locked-loop is an electronic circuit comprising a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched.
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