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computing device
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2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
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US-10637533-B2
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US-9159419-A1
US-9208071-A1
US-20200098728-A1
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US-20130279232-A1
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OPT-9
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ONSO3305US - Onsemi346
GTS-3DES
FLO-4
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KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
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FSP1845
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Placeholder App
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KBR-1 1400.2.623
PER-13PROV
PAT-3
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RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
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JBR-1
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PON-1PROV, 2PROV, 3PROV
PER-33
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MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
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BRT-PAT-1
TMC-PAT-5
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71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
App Docket
Created Date
Full Desc
FIG. 1 depicts a system 100 comprising a hybrid die 150. In certain embodiments, the hybrid die 150 may include phase change memory (PCM) and magnetoresistive random access memory (MRAM). In the depicted embodiment, the system includes a computing device 110. In various embodiments, a computing device 110 may refer to any electronic device capable computing by performing arithmetic or logical operations on electronic data. For example, a computing device 110 may be a server, a workstation, a desktop computer, a laptop computer, a tablet, a smartphone, a control system for another electronic device, a network attached storage device, a block device on a storage area network, a router, a network switch, or the like. In certain embodiments, a computing device 110 may include a non-transitory, computer readable storage medium that stores computer readable instructions configured to cause the computing device 110 to perform steps of one or more of the methods disclosed herein. In the depicted embodiment, the computing device 110 includes a processor 115, a memory 130, and storage 140. In various embodiments, a processor 115 may refer to any electronic element that carries out the arithmetic or logical operations performed by the computing device. For example, in one embodiment, the processor 115 may be a general-purpose processor that executes stored program code. In another embodiment, a processor 115 may be a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or the like, that operates on data stored by the memory 130 and/or the storage 140. In a certain embodiment, a processor 115 may be a controller for a storage device (e.g., on a storage area network) a networking device, or the like. In the depicted embodiment, the processor 115 includes a cache 120. In various embodiments, a cache 120 may store data for use by the processor 115. In certain embodiments, a cache 120 may be smaller and faster than the memory 130, and may duplicate data in frequently-used locations of the memory 130, or the like. In certain embodiments, a processor 115 may include a plurality of caches 120. In various embodiments, a cache 120 may include one or more types of memory media for storing data, such as static random access memory (SRAM) 122, the hybrid die 150, or the like. For example, in one embodiment, a cache 120 may include SRAM 122. In another embodiment, a cache 120 may include the hybrid die 150. In a certain embodiment, a cache 120 may include a combination of SRAM 122, the hybrid die 150, and/or other memory media types. The memory 130, in one embodiment, is coupled to the processor 115 by a memory bus 135. In certain embodiments, the memory 130 may store data that is directly addressable by the processor 115. In various embodiments, a memory 130 may include one or more types of memory media for storing data, such as dynamic random access memory (DRAM) 132, the hybrid die 150, or the like. For example, in one embodiment, a memory 130 may include DRAM 132. In another embodiment, a memory 130 may include the hybrid die 150. In a certain embodiment, a memory 130 may include a combination of DRAM 132, the hybrid die 150, and/or other memory media types. The storage 140, in one embodiment, is coupled to the processor 115 by a storage bus 145. In certain embodiments, the storage bus 145 may be a peripheral bus of the computing device 110, such as a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (SATA) bus, a parallel Advanced Technology Attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like. In various embodiments, the storage 140 may store data that is not directly addressable by the processor 115, but that may be accessed via one or more storage controllers. In certain embodiments, the storage 140 may be larger than the memory 130. In various embodiments, a storage 140 may include one or more types of storage media for storing data, such as a hard disk drive, NAND flash memory 142, the hybrid die 150, or the like. For example, in one embodiment, a storage 140 may include NAND flash memory 142. In another embodiment, a storage 140 may include the hybrid die 150. In a certain embodiment, a storage 140 may include a combination of NAND flash memory 142, the hybrid die 150, and/or other storage media types.
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