Dave's PCF WIP: Paragraphs

Paragraphs

Actions	Matter	Content	Para #	Notes	Modified
View Edit Delete	US9632727B2	Claim 6.The apparatus of claim 1, wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system, wherein the bus interface comprises one of a universal serial bus interface, an Institute of Electrical and Electronics Engineers 1394 bus interface, an external Serial Advanced Technology Attachment bus interface, a Peripheral Component Interconnect (PCI) bus interface, a PCI Express bus interface, an InfiniBand interface, an Integrated Drive Electronics (IDE) bus interface, an AT Attachment (ATA) interface, a Parallel ATA (PATA) interface, a Serial ATA (SATA) bus interface, an external SATA bus interface, a Small Computer System Interface (SCSI) bus interface, an internet SCSI interface, and a Fibre Channel interface.	296	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 7.A system, comprising:	297	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	means for controlling a solid-state storage medium, comprising,	298	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium, and	299	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium; and	300	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium, wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings; and	301	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings.	302	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 8.The system of claim 7, further comprising means for providing a storage interface to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium.	303	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 9.The system of claim 7, wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings, the entry indicating a mapping between the identified logical block and the particular storage block.	304	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 10.The system of claim 7, further comprising means for indicating that data stored on the particular physical storage block can be erased from the solid-state storage medium.	305	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 11.The system of claim 7, further comprising means for recording that the identified logical block is unmapped on the solid-state storage medium.	306	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 12.A non-volatile solid-state storage system, comprising:	307	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	a storage interface configured to communicate with a storage client;	308	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	a storage processor coupled to the storage interface;	309	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	a flash memory device coupled to the storage processor; and	310	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	a logical-to-physical translation layer maintained by the storage processor, wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device, wherein the storage processor is configured to:	311	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	receive, from the storage client through the storage interface, an empty-block directive command and a range of logical block addresses,	312	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved, and	313	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	store persistent data on the flash memory device, the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client.	314	Added by DJM 3 2021	3/24/21, 12:00 AM
View Edit Delete	US9632727B2	Claim 13.The system of claim 12, wherein the logical-to-physical translation layer is stored in the flash memory device.	315	Added by DJM 3 2021	3/24/21, 12:00 AM

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