Paragraph 246
Paragraph 246
Application
Calibrating non-volatile memory read thresholds
Matter Number
US10998041B1
Paragraph Number
246
Application Number
16869424
Reference Case 1
US10998041B1
Reference Case 2
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Created
12/22/21, 12:00 AM
Modified
12/22/21, 12:00 AM
Id
6,486
Content
The processor(s) 1512 communicate with a number of peripheral devices via a bus subsystem 1516. These peripheral devices may include input device(s) 1508, output device(s) 1510, communication network interface 1506, and the storage subsystem 1514. The storage subsystem 1514, in one embodiment, comprises one or more storage devices and/or one or more memory devices.
Notes
Added by DJM 12 2021