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The bank controllers 418 typically receive commands from the queues 410, 412, 414, 416 and generate appropriate subcommands. For example, the bank-0 write queue 412a may receive a command to write a page of data packets to bank-0 214a. The bank-0 controller 418a may receive the write command at an appropriate time and may generate one or more write subcommands for each data packet stored in the write buffer 320 to be written to the page in bank-0 214a. For example, bank-0 controller 418a may generate commands to validate the status of bank 0 214a and the solid-state storage array 216, select the appropriate location for writing one or more data packets, clear the input buffers within the solid-state storage memory array 216, transfer the one or more data packets to the input buffers, program the input buffers into the selected location, verify that the data was correctly programmed, and if program failures occur do one or more of interrupting the master controller 224, retrying the write to the same physical location, and retrying the write to a different physical location. Additionally, in conjunction with example write command, the storage bus controller 348 will cause the one or more commands to multiplied to each of the each of the storage I/O buses 210a-n with the logical address of the command mapped to a first physical addresses for storage I/O bus 210a, and mapped to a second physical address for storage I/O bus 210b, and so forth as further described below.

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<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">The bank controllers </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve"> typically receive commands from the queues </w:t></w:r><w:r><w:t>410</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>412</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>414</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>416</w:t></w:r><w:r><w:t xml:space="preserve"> and generate appropriate subcommands. For example, the bank-0 write queue </w:t></w:r><w:r><w:t>412</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">may receive a command to write a page of data packets to bank-0 </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">. The bank-0 controller </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">may receive the write command at an appropriate time and may generate one or more write subcommands for each data packet stored in the write buffer </w:t></w:r><w:r><w:t>320</w:t></w:r><w:r><w:t xml:space="preserve"> to be written to the page in bank-0 </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">. For example, bank-0 controller </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">may generate commands to validate the status of bank 0 </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">and the solid-state storage array </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, select the appropriate location for writing one or more data packets, clear the input buffers within the solid-state storage memory array </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, transfer the one or more data packets to the input buffers, program the input buffers into the selected location, verify that the data was correctly programmed, and if program failures occur do one or more of interrupting the master controller </w:t></w:r><w:r><w:t>224</w:t></w:r><w:r><w:t xml:space="preserve">, retrying the write to the same physical location, and retrying the write to a different physical location. Additionally, in conjunction with example write command, the storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> will cause the one or more commands to multiplied to each of the each of the storage I/O buses </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t xml:space="preserve">n </w:t></w:r><w:r><w:t xml:space="preserve">with the logical address of the command mapped to a first physical addresses for storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, and mapped to a second physical address for storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t>b</w:t></w:r><w:r><w:t>, and so forth as further described below.</w:t></w:r></w:p>