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For example, during a write operation on bank-0 the bus arbiter 420 selects the bank-0 controller 418a which may have a write command or a series of write sub-commands on the top of its queue which cause the storage bus controller 348 to execute the following sequence. The bus arbiter 420 forwards the write command to the storage bus controller 348, which sets up a write command by selecting bank-0214a through the storage control bus 212, sending a command to clear the input buffers of the solid-state storage elements 110 associated with the bank-0214a, and sending a command to validate the status of the solid-state storage elements 216, 218, 220 associated with the bank-0214a. The storage bus controller 348 then transmits a write subcommand on the storage I/O bus 210, which contains the physical addresses including the address of the logical erase block for each individual physical erase solid-stage storage element 216a-m as mapped from the logical erase block address. The storage bus controller 348 then muxes the write buffer 320 through the write sync buffer 308 to the storage I/O bus 210 through the MUX 350 and streams write data to the appropriate page. When the page is full, then storage bus controller 348 causes the solid-state storage elements 216a-m associated with the bank-0214a to program the input buffer to the memory cells within the solid-state storage elements 216a-m. Finally, the storage bus controller 348 validates the status to ensure that page was correctly programmed.

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<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t>For example, during a write operation on bank-</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t xml:space="preserve"> the bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve"> selects the bank-</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t xml:space="preserve"> controller </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">which may have a write command or a series of write sub-commands on the top of its queue which cause the storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> to execute the following sequence. The bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve"> forwards the write command to the storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t>, which sets up a write command by selecting bank-</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">through the storage control bus </w:t></w:r><w:r><w:t>212</w:t></w:r><w:r><w:t xml:space="preserve">, sending a command to clear the input buffers of the solid-state storage elements </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> associated with the bank-</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, and sending a command to validate the status of the solid-state storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t xml:space="preserve"> associated with the bank-</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">. The storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> then transmits a write subcommand on the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve">, which contains the physical addresses including the address of the logical erase block for each individual physical erase solid-stage storage element </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t xml:space="preserve">m </w:t></w:r><w:r><w:t xml:space="preserve">as mapped from the logical erase block address. The storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> then muxes the write buffer </w:t></w:r><w:r><w:t>320</w:t></w:r><w:r><w:t xml:space="preserve"> through the write sync buffer </w:t></w:r><w:r><w:t>308</w:t></w:r><w:r><w:t xml:space="preserve"> to the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> through the MUX </w:t></w:r><w:r><w:t>350</w:t></w:r><w:r><w:t xml:space="preserve"> and streams write data to the appropriate page. When the page is full, then storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> causes the solid-state storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t xml:space="preserve">m </w:t></w:r><w:r><w:t>associated with the bank-</w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">a </w:t></w:r><w:r><w:t xml:space="preserve">to program the input buffer to the memory cells within the solid-state storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>m</w:t></w:r><w:r><w:t xml:space="preserve">. Finally, the storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> validates the status to ensure that page was correctly programmed.</w:t></w:r></w:p>