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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
182
Application Number
11952091
Reference Case 1
Reference Case 2
Content
Typically, bus arbiter 420 selects from among the bank controllers 418 and pulls subcommands from output queues within the bank controllers 418 and forwards these to the Storage Bus Controller 348 in a sequence that optimizes the performance of the banks 214. In another embodiment, the bus arbiter 420 may respond to a high level interrupt and modify the normal selection criteria. In another embodiment, the master controller 224 can control the bus arbiter 420 through the control and status registers 340. One of skill in the art will recognize other means by which the bus arbiter 420 may control and interleave the sequence of commands from the bank controllers 418 to the solid-state storage 110.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">Typically, bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve"> selects from among the bank controllers </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve"> and pulls subcommands from output queues within the bank controllers </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve"> and forwards these to the Storage Bus Controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> in a sequence that optimizes the performance of the banks </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">. In another embodiment, the bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve"> may respond to a high level interrupt and modify the normal selection criteria. In another embodiment, the master controller </w:t></w:r><w:r><w:t>224</w:t></w:r><w:r><w:t xml:space="preserve"> can control the bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve"> through the control and status registers </w:t></w:r><w:r><w:t>340</w:t></w:r><w:r><w:t xml:space="preserve">. One of skill in the art will recognize other means by which the bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve"> may control and interleave the sequence of commands from the bank controllers </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t xml:space="preserve"> to the solid-state storage </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t>.</w:t></w:r></w:p>
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