Dave's Patent Content Factory
Applications
Terms
Paragraphs
Claims
Docket
Logout
About
Paragraph #3,086
Edit Paragraph
View
List Paragraphs
Delete
Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
173
Application Number
11952091
Reference Case 1
Reference Case 2
Content
FIG. 4A is a schematic block diagram illustrating one embodiment 400 of a bank interleave controller 344 in the solid-state storage controller 104 in accordance with the present invention. The bank interleave controller 344 is connected to the control and status registers 340 and to the storage I/O bus 210 and storage control bus 212 through the MUX 350, storage bus controller 348, and synchronization buffer 346, which are described below. The bank interleave controller 344 includes a read agent 402, a write agent 404, an erase agent 406, a management agent 408, read queues 410a-n, write queues 412a-n, erase queues 414a-n, and management queues 416a-n for the banks 214 in the solid-state storage 110, bank controllers 418a-n, a bus arbiter 420, and a status MUX 422, which are described below. The storage bus controller 348 includes a mapping module 424 with a remapping module 430, a status capture module 426, and a NAND bus controller 428, which are described below.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t>FIG. 4A</w:t></w:r><w:r><w:t xml:space="preserve"> is a schematic block diagram illustrating one embodiment </w:t></w:r><w:r><w:t>400</w:t></w:r><w:r><w:t xml:space="preserve"> of a bank interleave controller </w:t></w:r><w:r><w:t>344</w:t></w:r><w:r><w:t xml:space="preserve"> in the solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> in accordance with the present invention. The bank interleave controller </w:t></w:r><w:r><w:t>344</w:t></w:r><w:r><w:t xml:space="preserve"> is connected to the control and status registers </w:t></w:r><w:r><w:t>340</w:t></w:r><w:r><w:t xml:space="preserve"> and to the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> and storage control bus </w:t></w:r><w:r><w:t>212</w:t></w:r><w:r><w:t xml:space="preserve"> through the MUX </w:t></w:r><w:r><w:t>350</w:t></w:r><w:r><w:t xml:space="preserve">, storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve">, and synchronization buffer </w:t></w:r><w:r><w:t>346</w:t></w:r><w:r><w:t xml:space="preserve">, which are described below. The bank interleave controller </w:t></w:r><w:r><w:t>344</w:t></w:r><w:r><w:t xml:space="preserve"> includes a read agent </w:t></w:r><w:r><w:t>402</w:t></w:r><w:r><w:t xml:space="preserve">, a write agent </w:t></w:r><w:r><w:t>404</w:t></w:r><w:r><w:t xml:space="preserve">, an erase agent </w:t></w:r><w:r><w:t>406</w:t></w:r><w:r><w:t xml:space="preserve">, a management agent </w:t></w:r><w:r><w:t>408</w:t></w:r><w:r><w:t xml:space="preserve">, read queues </w:t></w:r><w:r><w:t>410</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>n</w:t></w:r><w:r><w:t xml:space="preserve">, write queues </w:t></w:r><w:r><w:t>412</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>n</w:t></w:r><w:r><w:t xml:space="preserve">, erase queues </w:t></w:r><w:r><w:t>414</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>n</w:t></w:r><w:r><w:t xml:space="preserve">, and management queues </w:t></w:r><w:r><w:t>416</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t xml:space="preserve">n </w:t></w:r><w:r><w:t xml:space="preserve">for the banks </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve"> in the solid-state storage </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve">, bank controllers </w:t></w:r><w:r><w:t>418</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>n</w:t></w:r><w:r><w:t xml:space="preserve">, a bus arbiter </w:t></w:r><w:r><w:t>420</w:t></w:r><w:r><w:t xml:space="preserve">, and a status MUX </w:t></w:r><w:r><w:t>422</w:t></w:r><w:r><w:t xml:space="preserve">, which are described below. The storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve"> includes a mapping module </w:t></w:r><w:r><w:t>424</w:t></w:r><w:r><w:t xml:space="preserve"> with a remapping module </w:t></w:r><w:r><w:t>430</w:t></w:r><w:r><w:t xml:space="preserve">, a status capture module </w:t></w:r><w:r><w:t>426</w:t></w:r><w:r><w:t xml:space="preserve">, and a NAND bus controller </w:t></w:r><w:r><w:t>428</w:t></w:r><w:r><w:t>, which are described below.</w:t></w:r></w:p>
Submit