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In one embodiment, the write pipeline 106 includes an input buffer 306 that receives a data segment to be written to the solid-state storage 110 and stores the incoming data segments until the next stage of the write data pipeline 106, such as the packetizer 302 (or other stage for a more complex write data pipeline 106) is ready to process the next data segment. The input buffer 306 typically allows for discrepancies between the rate data segments are received and processed by the write data pipeline 106 using an appropriately sized data buffer. The input buffer 306 also allows the data bus 204 to transfer data to the write data pipeline 106 at rates greater than can be sustained by the write data pipeline 106 in order to improve efficiency of operation of the data bus 204. Typically when the write data pipeline 106 does not include an input buffer 306, a buffering function is performed elsewhere, such as in the solid-state storage device 102 but outside the write data pipeline 106, in the computer 112, such as within a network interface card (“NIC”), or at another device, for example when using remote direct memory access (“RDMA”).

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<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">In one embodiment, the write pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> includes an input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve"> that receives a data segment to be written to the solid-state storage </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> and stores the incoming data segments until the next stage of the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve">, such as the packetizer </w:t></w:r><w:r><w:t>302</w:t></w:r><w:r><w:t xml:space="preserve"> (or other stage for a more complex write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve">) is ready to process the next data segment. The input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve"> typically allows for discrepancies between the rate data segments are received and processed by the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> using an appropriately sized data buffer. The input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve"> also allows the data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve"> to transfer data to the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> at rates greater than can be sustained by the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> in order to improve efficiency of operation of the data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">. Typically when the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> does not include an input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve">, a buffering function is performed elsewhere, such as in the solid-state storage device </w:t></w:r><w:r><w:t>102</w:t></w:r><w:r><w:t xml:space="preserve"> but outside the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve">, in the computer </w:t></w:r><w:r><w:t>112</w:t></w:r><w:r><w:t>, such as within a network interface card (“NIC”), or at another device, for example when using remote direct memory access (“RDMA”).</w:t></w:r></w:p>