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FIG. 3 is a schematic block diagram illustrating one embodiment 300 of a solid-state storage controller 104 with a write data pipeline 106 and a read data pipeline 108 in a solid-state storage device 102 in accordance with the present invention. The embodiment 300 includes a data bus 204, a local bus 206, and buffer control 208, which are substantially similar to those described in relation to the solid-state storage device controller 202 of FIG. 2. The write data pipeline 106 includes a packetizer 302 and an error-correcting code (“ECC”) generator 304. In other embodiments, the write data pipeline 106 includes an input buffer 306, a write synchronization buffer 308, a write program module 310, a compression module 312, an encryption module 314, a garbage collector bypass 316 (with a portion within the read data pipeline 108), a media encryption module 318, and a write buffer 320. The read data pipeline 108 includes a read synchronization buffer 328, an ECC correction module 322, a depacketizer 324, an alignment module 326, and an output buffer 330. In other embodiments, the read data pipeline 108 may include a media decryption module 332, a portion of the garbage collector bypass 316, a decryption module 334, a decompression module 336, and a read program module 338. The solid-state storage controller 104 may also include control and status registers 340 and control queues 342, a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350. The components of the solid-state controller 104 and associated write data pipeline 106 and read data pipeline 108 are described below. In other embodiments, synchronous solid-state storage 110 may be used and synchronization buffers 308328 may be eliminated.

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<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t>FIG. 3</w:t></w:r><w:r><w:t xml:space="preserve"> is a schematic block diagram illustrating one embodiment </w:t></w:r><w:r><w:t>300</w:t></w:r><w:r><w:t xml:space="preserve"> of a solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> with a write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> and a read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> in a solid-state storage device </w:t></w:r><w:r><w:t>102</w:t></w:r><w:r><w:t xml:space="preserve"> in accordance with the present invention. The embodiment </w:t></w:r><w:r><w:t>300</w:t></w:r><w:r><w:t xml:space="preserve"> includes a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">, a local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve">, and buffer control </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve">, which are substantially similar to those described in relation to the solid-state storage device controller </w:t></w:r><w:r><w:t>202</w:t></w:r><w:r><w:t xml:space="preserve"> of </w:t></w:r><w:r><w:t>FIG. 2</w:t></w:r><w:r><w:t xml:space="preserve">. The write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> includes a packetizer </w:t></w:r><w:r><w:t>302</w:t></w:r><w:r><w:t xml:space="preserve"> and an error-correcting code (“ECC”) generator </w:t></w:r><w:r><w:t>304</w:t></w:r><w:r><w:t xml:space="preserve">. In other embodiments, the write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> includes an input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve">, a write synchronization buffer </w:t></w:r><w:r><w:t>308</w:t></w:r><w:r><w:t xml:space="preserve">, a write program module </w:t></w:r><w:r><w:t>310</w:t></w:r><w:r><w:t xml:space="preserve">, a compression module </w:t></w:r><w:r><w:t>312</w:t></w:r><w:r><w:t xml:space="preserve">, an encryption module </w:t></w:r><w:r><w:t>314</w:t></w:r><w:r><w:t xml:space="preserve">, a garbage collector bypass </w:t></w:r><w:r><w:t>316</w:t></w:r><w:r><w:t xml:space="preserve"> (with a portion within the read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve">), a media encryption module </w:t></w:r><w:r><w:t>318</w:t></w:r><w:r><w:t xml:space="preserve">, and a write buffer </w:t></w:r><w:r><w:t>320</w:t></w:r><w:r><w:t xml:space="preserve">. The read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> includes a read synchronization buffer </w:t></w:r><w:r><w:t>328</w:t></w:r><w:r><w:t xml:space="preserve">, an ECC correction module </w:t></w:r><w:r><w:t>322</w:t></w:r><w:r><w:t xml:space="preserve">, a depacketizer </w:t></w:r><w:r><w:t>324</w:t></w:r><w:r><w:t xml:space="preserve">, an alignment module </w:t></w:r><w:r><w:t>326</w:t></w:r><w:r><w:t xml:space="preserve">, and an output buffer </w:t></w:r><w:r><w:t>330</w:t></w:r><w:r><w:t xml:space="preserve">. In other embodiments, the read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> may include a media decryption module </w:t></w:r><w:r><w:t>332</w:t></w:r><w:r><w:t xml:space="preserve">, a portion of the garbage collector bypass </w:t></w:r><w:r><w:t>316</w:t></w:r><w:r><w:t xml:space="preserve">, a decryption module </w:t></w:r><w:r><w:t>334</w:t></w:r><w:r><w:t xml:space="preserve">, a decompression module </w:t></w:r><w:r><w:t>336</w:t></w:r><w:r><w:t xml:space="preserve">, and a read program module </w:t></w:r><w:r><w:t>338</w:t></w:r><w:r><w:t xml:space="preserve">. The solid-state storage controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> may also include control and status registers </w:t></w:r><w:r><w:t>340</w:t></w:r><w:r><w:t xml:space="preserve"> and control queues </w:t></w:r><w:r><w:t>342</w:t></w:r><w:r><w:t xml:space="preserve">, a bank interleave controller </w:t></w:r><w:r><w:t>344</w:t></w:r><w:r><w:t xml:space="preserve">, a synchronization buffer </w:t></w:r><w:r><w:t>346</w:t></w:r><w:r><w:t xml:space="preserve">, a storage bus controller </w:t></w:r><w:r><w:t>348</w:t></w:r><w:r><w:t xml:space="preserve">, and a multiplexer (“MUX”) </w:t></w:r><w:r><w:t>350</w:t></w:r><w:r><w:t xml:space="preserve">. The components of the solid-state controller </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> and associated write data pipeline </w:t></w:r><w:r><w:t>106</w:t></w:r><w:r><w:t xml:space="preserve"> and read data pipeline </w:t></w:r><w:r><w:t>108</w:t></w:r><w:r><w:t xml:space="preserve"> are described below. In other embodiments, synchronous solid-state storage </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> may be used and synchronization buffers </w:t></w:r><w:r><w:t>308</w:t></w:r><w:r><w:t>328</w:t></w:r><w:r><w:t xml:space="preserve"> may be eliminated.</w:t></w:r></w:p>