Dave's PCF WIP: Paragraphs

Paragraph #3,024

Edit Paragraph

View List Paragraphs Delete

Application

Matter Number

Paragraph Number

Application Number

Reference Case 1

Reference Case 2

Content

Data may also be communicated to the solid-state storage controller(s) 104 from a requesting device 155 through the system bus 240, bridge 238, local bus 206, buffer(s) 222, and finally over a data bus 204. The data bus 204 typically is connected to one or more buffers 222a-n controlled with a buffer controller 208. The buffer controller 208 typically controls transfer of data from the local bus 206 to the buffers 222 and through the data bus 204 to the pipeline input buffer 306 and output buffer 330. The buffer controller 208 typically controls how data arriving from a requesting device 155 can be temporarily stored in a buffer 222 and then transferred onto a data bus 204, or vice versa, to account for different clock domains, to prevent data collisions, etc. The buffer controller 208 typically works in conjunction with the master controller 224 to coordinate data flow. As data arrives, the data will arrive on the system bus 240, be transferred to the local bus 206 through a bridge 238.

Notes

Raw Data

<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">Data may also be communicated to the solid-state storage controller(s) </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> from a requesting device </w:t></w:r><w:r><w:t>155</w:t></w:r><w:r><w:t xml:space="preserve"> through the system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve">, bridge </w:t></w:r><w:r><w:t>238</w:t></w:r><w:r><w:t xml:space="preserve">, local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve">, buffer(s) </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t xml:space="preserve">, and finally over a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">. The data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve"> typically is connected to one or more buffers </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t xml:space="preserve">n </w:t></w:r><w:r><w:t xml:space="preserve">controlled with a buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve">. The buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve"> typically controls transfer of data from the local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve"> to the buffers </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t xml:space="preserve"> and through the data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve"> to the pipeline input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve"> and output buffer </w:t></w:r><w:r><w:t>330</w:t></w:r><w:r><w:t xml:space="preserve">. The buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve"> typically controls how data arriving from a requesting device </w:t></w:r><w:r><w:t>155</w:t></w:r><w:r><w:t xml:space="preserve"> can be temporarily stored in a buffer </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t xml:space="preserve"> and then transferred onto a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">, or vice versa, to account for different clock domains, to prevent data collisions, etc. The buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve"> typically works in conjunction with the master controller </w:t></w:r><w:r><w:t>224</w:t></w:r><w:r><w:t xml:space="preserve"> to coordinate data flow. As data arrives, the data will arrive on the system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve">, be transferred to the local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve"> through a bridge </w:t></w:r><w:r><w:t>238</w:t></w:r><w:r><w:t>.</w:t></w:r></w:p>