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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
109
Application Number
11952091
Reference Case 1
Reference Case 2
Content
In various embodiments, the solid-state storage device controller 202 also includes a data bus 204, a local bus 206, a buffer controller 208, buffers 0-N 222a-n, a master controller 224, a direct memory access (“DMA”) controller 226, a memory controller 228, a dynamic memory array 230, a static random memory array 232, a management controller 234, a management bus 236, a bridge 238 to a system bus 240, and miscellaneous logic 242, which are described below. In other embodiments, the system bus 240 is coupled to one or more network interface cards (“NICs”) 244, some of which may include remote DMA (“RDMA”) controllers 246, one or more central processing unit (“CPU”) 248, one or more external memory controllers 250 and associated external memory arrays 252, one or more storage controllers 254, peer controllers 256, and application specific processors 258, which are described below. The components 244-258 connected to the system bus 240 may be located in the computer 112 or may be other devices.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">In various embodiments, the solid-state storage device controller </w:t></w:r><w:r><w:t>202</w:t></w:r><w:r><w:t xml:space="preserve"> also includes a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">, a local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve">, a buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve">, buffers </w:t></w:r><w:r><w:t>0</w:t></w:r><w:r><w:t xml:space="preserve">-N </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>n</w:t></w:r><w:r><w:t xml:space="preserve">, a master controller </w:t></w:r><w:r><w:t>224</w:t></w:r><w:r><w:t xml:space="preserve">, a direct memory access (“DMA”) controller </w:t></w:r><w:r><w:t>226</w:t></w:r><w:r><w:t xml:space="preserve">, a memory controller </w:t></w:r><w:r><w:t>228</w:t></w:r><w:r><w:t xml:space="preserve">, a dynamic memory array </w:t></w:r><w:r><w:t>230</w:t></w:r><w:r><w:t xml:space="preserve">, a static random memory array </w:t></w:r><w:r><w:t>232</w:t></w:r><w:r><w:t xml:space="preserve">, a management controller </w:t></w:r><w:r><w:t>234</w:t></w:r><w:r><w:t xml:space="preserve">, a management bus </w:t></w:r><w:r><w:t>236</w:t></w:r><w:r><w:t xml:space="preserve">, a bridge </w:t></w:r><w:r><w:t>238</w:t></w:r><w:r><w:t xml:space="preserve"> to a system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve">, and miscellaneous logic </w:t></w:r><w:r><w:t>242</w:t></w:r><w:r><w:t xml:space="preserve">, which are described below. In other embodiments, the system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve"> is coupled to one or more network interface cards (“NICs”) </w:t></w:r><w:r><w:t>244</w:t></w:r><w:r><w:t xml:space="preserve">, some of which may include remote DMA (“RDMA”) controllers </w:t></w:r><w:r><w:t>246</w:t></w:r><w:r><w:t xml:space="preserve">, one or more central processing unit (“CPU”) </w:t></w:r><w:r><w:t>248</w:t></w:r><w:r><w:t xml:space="preserve">, one or more external memory controllers </w:t></w:r><w:r><w:t>250</w:t></w:r><w:r><w:t xml:space="preserve"> and associated external memory arrays </w:t></w:r><w:r><w:t>252</w:t></w:r><w:r><w:t xml:space="preserve">, one or more storage controllers </w:t></w:r><w:r><w:t>254</w:t></w:r><w:r><w:t xml:space="preserve">, peer controllers </w:t></w:r><w:r><w:t>256</w:t></w:r><w:r><w:t xml:space="preserve">, and application specific processors </w:t></w:r><w:r><w:t>258</w:t></w:r><w:r><w:t xml:space="preserve">, which are described below. The components </w:t></w:r><w:r><w:t>244</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t>258</w:t></w:r><w:r><w:t xml:space="preserve"> connected to the system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve"> may be located in the computer </w:t></w:r><w:r><w:t>112</w:t></w:r><w:r><w:t xml:space="preserve"> or may be other devices.</w:t></w:r></w:p>
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