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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
74
Application Number
13189402
Reference Case 1
Reference Case 2
Content
Data may also be communicated to the solid-state storage controller(s) 104 from a requesting device 155 through the system bus 240, bridge 238, local bus 206, buffer(s) 222, and finally over a data bus 204. The data bus 204 typically is connected to one or more buffers 222a-n controlled with a buffer controller 208. The buffer controller 208 typically controls transfer of data from the local bus 206 to the buffers 222 and through the data bus 204 to the pipeline input buffer 306 and output buffer 330. The buffer controller 208 typically controls how data arriving from a requesting device can be temporarily stored in a buffer 222 and then transferred onto a data bus 204, or vice versa, to account for different clock domains, to prevent data collisions, etc. The buffer controller 208 typically works in conjunction with the master controller 224 to coordinate data flow. As data arrives, the data will arrive on the system bus 240, be transferred to the local bus 206 through a bridge 238.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody1"/></w:pPr><w:r><w:t xml:space="preserve">Data may also be communicated to the solid-state storage controller(s) </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> from a requesting device </w:t></w:r><w:r><w:t>155</w:t></w:r><w:r><w:t xml:space="preserve"> through the system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve">, bridge </w:t></w:r><w:r><w:t>238</w:t></w:r><w:r><w:t xml:space="preserve">, local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve">, buffer(s) </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t xml:space="preserve">, and finally over a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">. The data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve"> typically is connected to one or more buffers </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>-</w:t></w:r><w:r><w:t xml:space="preserve">n </w:t></w:r><w:r><w:t xml:space="preserve">controlled with a buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve">. The buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve"> typically controls transfer of data from the local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve"> to the buffers </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t xml:space="preserve"> and through the data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve"> to the pipeline input buffer </w:t></w:r><w:r><w:t>306</w:t></w:r><w:r><w:t xml:space="preserve"> and output buffer </w:t></w:r><w:r><w:t>330</w:t></w:r><w:r><w:t xml:space="preserve">. The buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve"> typically controls how data arriving from a requesting device can be temporarily stored in a buffer </w:t></w:r><w:r><w:t>222</w:t></w:r><w:r><w:t xml:space="preserve"> and then transferred onto a data bus </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">, or vice versa, to account for different clock domains, to prevent data collisions, etc. The buffer controller </w:t></w:r><w:r><w:t>208</w:t></w:r><w:r><w:t xml:space="preserve"> typically works in conjunction with the master controller </w:t></w:r><w:r><w:t>224</w:t></w:r><w:r><w:t xml:space="preserve"> to coordinate data flow. As data arrives, the data will arrive on the system bus </w:t></w:r><w:r><w:t>240</w:t></w:r><w:r><w:t xml:space="preserve">, be transferred to the local bus </w:t></w:r><w:r><w:t>206</w:t></w:r><w:r><w:t xml:space="preserve"> through a bridge </w:t></w:r><w:r><w:t>238</w:t></w:r><w:r><w:t>.</w:t></w:r></w:p>
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