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Typically the solid-state storage controller(s) 104 communicate data to the solid-state storage media 110 over a storage I/O bus 210. In a typical embodiment where the solid-state storage is arranged in banks 214 and each bank 214 includes multiple storage elements 216a, 216b, 216m accessed in parallel, the storage I/O bus 210 is an array of busses, one for each column of storage elements 216, 218, 220 spanning the banks 214. As used herein, the term “storage I/O bus” may refer to one storage I/O bus 210 or an array of data independent busses 204. In one embodiment, each storage I/O bus 210 accessing a column of storage elements (e.g. 216a, 218a, 220a) may include a logical-to-physical mapping for storage divisions (e.g. erase blocks) accessed in a column of storage elements 216a, 218a, 220a. This mapping (or bad block remapping) allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem.

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<w:p><w:pPr><w:pStyle w:val="TPSBody1"/></w:pPr><w:r><w:t xml:space="preserve">Typically the solid-state storage controller(s) </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> communicate data to the solid-state storage media </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> over a storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve">. In a typical embodiment where the solid-state storage is arranged in banks </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve"> and each bank </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve"> includes multiple storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>b</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">m </w:t></w:r><w:r><w:t xml:space="preserve">accessed in parallel, the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> is an array of busses, one for each column of storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t xml:space="preserve"> spanning the banks </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">. As used herein, the term “storage I/O bus” may refer to one storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> or an array of data independent busses </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">. In one embodiment, each storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> accessing a column of storage elements (e.g. </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">) may include a logical-to-physical mapping for storage divisions (e.g. erase blocks) accessed in a column of storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>. This mapping (or bad block remapping) allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem.</w:t></w:r></w:p>