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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
73
Application Number
13189402
Reference Case 1
Reference Case 2
Content
Typically the solid-state storage controller(s) 104 communicate data to the solid-state storage media 110 over a storage I/O bus 210. In a typical embodiment where the solid-state storage is arranged in banks 214 and each bank 214 includes multiple storage elements 216a, 216b, 216m accessed in parallel, the storage I/O bus 210 is an array of busses, one for each column of storage elements 216, 218, 220 spanning the banks 214. As used herein, the term “storage I/O bus” may refer to one storage I/O bus 210 or an array of data independent busses 204. In one embodiment, each storage I/O bus 210 accessing a column of storage elements (e.g. 216a, 218a, 220a) may include a logical-to-physical mapping for storage divisions (e.g. erase blocks) accessed in a column of storage elements 216a, 218a, 220a. This mapping (or bad block remapping) allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem.
Notes
Added by DJM 3 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody1"/></w:pPr><w:r><w:t xml:space="preserve">Typically the solid-state storage controller(s) </w:t></w:r><w:r><w:t>104</w:t></w:r><w:r><w:t xml:space="preserve"> communicate data to the solid-state storage media </w:t></w:r><w:r><w:t>110</w:t></w:r><w:r><w:t xml:space="preserve"> over a storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve">. In a typical embodiment where the solid-state storage is arranged in banks </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve"> and each bank </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve"> includes multiple storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>b</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">m </w:t></w:r><w:r><w:t xml:space="preserve">accessed in parallel, the storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> is an array of busses, one for each column of storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t xml:space="preserve"> spanning the banks </w:t></w:r><w:r><w:t>214</w:t></w:r><w:r><w:t xml:space="preserve">. As used herein, the term “storage I/O bus” may refer to one storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> or an array of data independent busses </w:t></w:r><w:r><w:t>204</w:t></w:r><w:r><w:t xml:space="preserve">. In one embodiment, each storage I/O bus </w:t></w:r><w:r><w:t>210</w:t></w:r><w:r><w:t xml:space="preserve"> accessing a column of storage elements (e.g. </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">) may include a logical-to-physical mapping for storage divisions (e.g. erase blocks) accessed in a column of storage elements </w:t></w:r><w:r><w:t>216</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>218</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t xml:space="preserve">, </w:t></w:r><w:r><w:t>220</w:t></w:r><w:r><w:t>a</w:t></w:r><w:r><w:t>. This mapping (or bad block remapping) allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem.</w:t></w:r></w:p>
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