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Application
2380.2.01
US-20150012794-A1
US-20150205664-A1
US-20100023800-A1
US-8737141-A1
US-10157004-B2
US10007433A1
US-9159419-B2
US-10114589-A1
US-10134728-A1
US-20200065270-A1
US-10637533-B2
US-9927986-A1
US-8380915-A1
US-9159419-A1
US-9208071-A1
US-20200098728-A1
US-10643676-A1
US-10468073-B2
US-10283200-A1
US-10461965-B1
US-20130279232-A1
US-8892980-B2
US9632727A1
US10558561A1
US20100023800A1
US7230213A1
OPT-9
FLO-2
FLO-5PROV
ONSO3175(B) - Onsemi378
ONSO3305US - Onsemi346
GTS-3DES
FLO-4
US8762658B2
US8533406B2
US9632727B2
KMN-1PROV
PAT-2
PER-8 PROV
PER-9 PROV
INS-4PROV
HAR-1
CES-16
NXT-5PROV NXT-5, 6, 7, 8
IPP-0051-US14 cross roads
FLO-7PROV
IMI-5PROV
IPP-0050-US35 nextremity
VIL-12
OPT-13
TOY-1
US10998041B1
FSP1845
US6559866B2
Placeholder App
PER-10
KBR-1 1400.2.623
PER-13PROV
PAT-3
US20030023453
RMS-1DES
SMG-1DES
FLO-5
US10318495
US10133662B2
PER-11
US20140066758
VIL-17
PER-17
JBR-1
PER-12
US11056880
US11302645
US20210407565
US11081191
PON-1PROV, 2PROV, 3PROV
PER-33
RMT-1PROV
PER-32
PER-34
MCC-1
FLO-10
PER-14
PER-19
PER-22
PER-18
PER-24
TMC-PAT-1
DAR-2
PER-23
TMC-PAT-4
PER-16
PER-4 DIV1
PER-20
PER-21
BRT-PAT-1
TMC-PAT-5
TMC-PAT-6PROV
BRT-PAT-2-PROV
71212.157.USU1
FPR-PAT-1-PROV
71212.158.USP1
RMT-1
DAR-1PROV
DAR-2PROV
PON-1PROV
PON-2PROV
PON-3PROV
PER-18PROV
TMC-1PROV
TMC-2PROV
PER-13PCT
PER-13
PER-16PROV
PER-14PROV
PER-34PROV
TMC-4PROV
TMC-3
PAS-1PROV
VEH-1
PER-29DES
TEST.001
E2E-TEST.001
TEST-001
TEST-002
TEST-003
TEST-004
ZED006
FSP1011
GAV-PAT-1-PROV
Matter Number
Paragraph Number
136
Application Number
14076579
Reference Case 1
Reference Case 2
Content
In one embodiment, for NAND flash media 122 or the like, a binary zero may be represented by a voltage below a read voltage threshold and a binary one may be represented by a voltage above the read voltage threshold. In one example, a data set may be stored with a known bias of 0.5, representing that the expected balance/bias of the data set should be one half binary ones, or DC balanced. In this example, the data set may be read from the storage cells and may gave a read balance/bias of 0.7, meaning that seventy percent of the data bits are binary ones. To determine the direction of deviation, in one embodiment, the DC balance module 404 subtracts the expected bias, 0.5, from the read bias of the data set, 0.7, for a direction of 0.2. The direction may be the entire result (e.g., “0.2”), the sign of the result (e.g., “positive”), a relationship (e.g., “greater than”), a direction, (e.g., “up”), or another indicator that represents the difference between the expected bias of 0.5 and the read bias of 0.7.
Notes
Added by DJM 2 2021
Raw Data
<w:p><w:pPr><w:pStyle w:val="TPSBody100"/></w:pPr><w:r><w:t xml:space="preserve">In one embodiment, for NAND flash media </w:t></w:r><w:r><w:t>122</w:t></w:r><w:r><w:t xml:space="preserve"> or the like, a binary zero may be represented by a voltage below a read voltage threshold and a binary one may be represented by a voltage above the read voltage threshold. In one example, a data set may be stored with a known bias of 0.5, representing that the expected balance/bias of the data set should be one half binary ones, or DC balanced. In this example, the data set may be read from the storage cells and may gave a read balance/bias of 0.7, meaning that seventy percent of the data bits are binary ones. To determine the direction of deviation, in one embodiment, the DC balance module </w:t></w:r><w:r><w:t>404</w:t></w:r><w:r><w:t xml:space="preserve"> subtracts the expected bias, 0.5, from the read bias of the data set, 0.7, for a direction of 0.2. The direction may be the entire result (e.g., “0.2”), the sign of the result (e.g., “positive”), a relationship (e.g., “greater than”), a direction, (e.g., “up”), or another indicator that represents the difference between the expected bias of 0.5 and the read bias of 0.7.</w:t></w:r></w:p>
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