{
    "matter": "US11081191",
    "document_type": "Patent terminology definitions",
    "definitions": [
        {
            "term": "Clock period",
            "definition": "“Clock period” is the time between an edge (e.g., either rising or falling) of a first clock pulse and the corresponding edge of the next clock pulse in sequence. The clock toggle rate is the time between the rising and falling edges of one clock pulse."
        },
        {
            "term": "Flash translation layer",
            "definition": "“Flash translation layer” refers to a logic component in a memory device involved in the writing of data, typically involved in operations such as logical address translation, memory page management, memory wear leveling, and memory garbage collection. Modern flash translation layers may be configured to perform these operations while minimizing write amplification, which is the ratio of the amount of data actually written when executing a write command, to the amount of data in the write command as issued to the memory device. In some implementations, some or all of the flash translation layer logic may be implemented on the host device."
        },
        {
            "term": "host device",
            "definition": "A “host device” is a device such as a computer system that issues memory commands to a service device, such as a memory device."
        },
        {
            "term": "memory array",
            "definition": "“Memory array” refers to a collection of memory cells, organized into an array of rows and columns. Memory arrays may be two or three dimensional"
        },
        {
            "term": "memory channel",
            "definition": "“Memory channel” refers to a communication path for data to and from a memory. Memory channels are typically operable in parallel with one another, increasing throughput of data to and from the memory. For example in a multi-die memory package comprising four NAND memory dies, in which each NAND die comprises two memory channels, there may be eight FLASH interface modules."
        },
        {
            "term": "Memory system",
            "definition": "“Memory system” refers to a memory device including a controller operable on at least one memory array. Memory systems typically include many other components as well, as known in the art."
        },
        {
            "term": "ODT resistors",
            "definition": "“ODT resistors” refers to resistors electrically coupled to a transmission line to configure the impedance experienced by signals transmitted on the transmission line. One or more ODT resistors may be configured in parallel on the transmission lines."
        },
        {
            "term": "performance requirement",
            "definition": "A “performance requirement” refers to a timing requirement, for example a completion time or latency limit imposed on a memory command or commands. The performance requirement may take the form of a latency requirement of the command or commands, or a throughput requirement (X commands must complete in Y amount of time), for example. A performance requirement may be inherent in a command based on design specifications, or explicitly configured by a host device providing the command."
        },
        {
            "term": "phase-locked-loop (PLL)",
            "definition": "\"Phase-locked-loop\" is logic that generates an output signal whose phase is related to the phase of an input signal. One example of a phase-locked-loop is an electronic circuit comprising a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched."
        },
        {
            "term": "Random-access commands",
            "definition": "“Random-access commands” refers to Memory commands targeting non-sequential addresses in a memory. Random-access commands are distinguished from serial or block commands, which target multiple contiguous addresses in memory."
        },
        {
            "term": "Resistor",
            "definition": "“Resistor” refers to any circuit element providing an impedance. Resistors include pure resistive elements and elements including some design-purpose inductance and capacitance. Resistors may be passive or active devices."
        },
        {
            "term": "solid state drive",
            "definition": "“solid state drive” refers to a memory device providing a large memory capacity utilizing non-volatile semi-conductor gates, such as NAND or NOR gate devices, where a memory device refers to any device providing data storage for another device. Examples of memory devices include solid state drives, hard disk drives, optical drives, and devices providing volatile memory storage such as dynamic random access memory (DRAM). Other examples of memory devices include memory cards, and Universal Serial Bus (USB) FLASH drives.\r\nSolid state drives may provide memory capacity on par with hard disk devices but with much higher performance. NAND flash memories in particular tend to have a lower price and a larger capacity relative to other non-volatile memory types (memory that retains its state in the absence of operating power)."
        },
        {
            "term": "switch",
            "definition": "“switch” refers to any device providing controllable changes in impedance between an open state of very high or effectively infinite impedance, and a closed state of very low or effectively zero impedance. Examples of switches are NMOS transistors and PMOS transistors, and mechanical switches."
        },
        {
            "term": "toggle rate",
            "definition": "“toggle rate” refers to the time between the rising and falling edges of a clock pulse, and hence for periodic clock pulses defines the frequency at which the clock signal can trigger other circuits."
        },
        {
            "term": "Workload",
            "definition": "“Workload” refers to the commands received by device and queued for execution, which may include commands currently undergoing execution. The workload can include not only a number of commands received and queued for execution, or expected to be received (e.g., based on hints provided by the host device), but also the types of commands and/or associated performance requirements of the commands."
        }
    ]
}